Merge zizzer:/bk/m5
[gem5.git] / dev / tsunami.cc
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /** @file
30 * Implementation of Tsunami platform.
31 */
32
33 #include <deque>
34 #include <string>
35 #include <vector>
36
37 #include "cpu/intr_control.hh"
38 #include "dev/simconsole.hh"
39 #include "dev/ide_ctrl.hh"
40 #include "dev/tsunami_cchip.hh"
41 #include "dev/tsunami_pchip.hh"
42 #include "dev/tsunami_io.hh"
43 #include "dev/tsunami.hh"
44 #include "dev/pciconfigall.hh"
45 #include "sim/builder.hh"
46 #include "sim/system.hh"
47
48 using namespace std;
49 //Should this be AlphaISA?
50 using namespace TheISA;
51
52 Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
53 PciConfigAll *pci)
54 : Platform(name, ic, pci), system(s)
55 {
56 // set the back pointer from the system to myself
57 system->platform = this;
58
59 for (int i = 0; i < Tsunami::Max_CPUs; i++)
60 intr_sum_type[i] = 0;
61 }
62
63 Tick
64 Tsunami::intrFrequency()
65 {
66 return io->frequency();
67 }
68
69 void
70 Tsunami::postConsoleInt()
71 {
72 io->postPIC(0x10);
73 }
74
75 void
76 Tsunami::clearConsoleInt()
77 {
78 io->clearPIC(0x10);
79 }
80
81 void
82 Tsunami::postPciInt(int line)
83 {
84 cchip->postDRIR(line);
85 }
86
87 void
88 Tsunami::clearPciInt(int line)
89 {
90 cchip->clearDRIR(line);
91 }
92
93 Addr
94 Tsunami::pciToDma(Addr pciAddr) const
95 {
96 return pchip->translatePciToDma(pciAddr);
97 }
98
99 void
100 Tsunami::serialize(std::ostream &os)
101 {
102 SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
103 }
104
105 void
106 Tsunami::unserialize(Checkpoint *cp, const std::string &section)
107 {
108 UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
109 }
110
111 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
112
113 SimObjectParam<System *> system;
114 SimObjectParam<IntrControl *> intrctrl;
115 SimObjectParam<PciConfigAll *> pciconfig;
116
117 END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
118
119 BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
120
121 INIT_PARAM(system, "system"),
122 INIT_PARAM(intrctrl, "interrupt controller"),
123 INIT_PARAM(pciconfig, "PCI configuration")
124
125 END_INIT_SIM_OBJECT_PARAMS(Tsunami)
126
127 CREATE_SIM_OBJECT(Tsunami)
128 {
129 return new Tsunami(getInstanceName(), system, intrctrl, pciconfig);
130 }
131
132 REGISTER_SIM_OBJECT("Tsunami", Tsunami)