dev/tsunami.hh

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /**
  30  * @file
  31  * Declaration of top level class for the Tsunami chipset. This class just
  32  * retains pointers to all its children so the children can communicate.
  33  */
  34
  35 #ifndef __TSUNAMI_HH__
  36 #define __TSUNAMI_HH__
  37
  38 #include "dev/platform.hh"
  39
  40 class IdeController;
  41 class TlaserClock;
  42 class NSGigE;
  43 class TsunamiCChip;
  44 class TsunamiPChip;
  45 class TsunamiIO;
  46 class PciConfigAll;
  47 class System;
  48
  49 /**
  50   * Top level class for Tsunami Chipset emulation.
  51   * This structure just contains pointers to all the
  52   * children so the children can commnicate to do the
  53   * read work
  54   */
  55
  56 class Tsunami : public Platform
  57 {
  58   public:
  59
  60     /** Max number of CPUs in a Tsunami */
  61     static const int Max_CPUs = 4;
  62
  63     /** Pointer to the system */
  64     System *system;
  65
  66     /** Pointer to the TsunamiIO device which has the RTC */
  67     TsunamiIO *io;
  68
  69     /** Pointer to the Tsunami CChip.
  70       * The chip contains some configuration information and
  71       * all the interrupt mask and status registers
  72       */
  73     TsunamiCChip *cchip;
  74
  75     /** Pointer to the Tsunami PChip.
  76       * The pchip is the interface to the PCI bus, in our case
  77       * it does not have to do much.
  78       */
  79     TsunamiPChip *pchip;
  80
  81     int intr_sum_type[Tsunami::Max_CPUs];
  82     int ipi_pending[Tsunami::Max_CPUs];
  83
  84   public:
  85     /**
  86       * Constructor for the Tsunami Class.
  87       * @param name name of the object
  88       * @param con pointer to the console
  89       * @param intrcontrol pointer to the interrupt controller
  90       * @param intrFreq frequency that interrupts happen
  91       */
  92     Tsunami(const std::string &name, System *s, IntrControl *intctrl,
  93             PciConfigAll *pci, int intrFreq);
  94
  95     /**
  96      * Return the interrupting frequency to AlphaAccess
  97      * @return frequency of RTC interrupts
  98      */
  99      virtual Tick intrFrequency();
 100
 101     /**
 102      * Cause the cpu to post a serial interrupt to the CPU.
 103      */
 104     virtual void postConsoleInt();
 105
 106     /**
 107      * Clear a posted CPU interrupt (id=55)
 108      */
 109     virtual void clearConsoleInt();
 110
 111     /**
 112      * Cause the chipset to post a cpi interrupt to the CPU.
 113      */
 114     virtual void postPciInt(int line);
 115
 116     /**
 117      * Clear a posted PCI->CPU interrupt
 118      */
 119     virtual void clearPciInt(int line);
 120
 121     virtual Addr pciToDma(Addr pciAddr) const;
 122
 123   /**
 124      * Serialize this object to the given output stream.
 125      * @param os The stream to serialize to.
 126      */
 127     virtual void serialize(std::ostream &os);
 128
 129     /**
 130      * Reconstruct the state of this object from a checkpoint.
 131      * @param cp The checkpoint use.
 132      * @param section The section name of this object
 133      */
 134     virtual void unserialize(Checkpoint *cp, const std::string &section);
 135 };
 136
 137 #endif // __TSUNAMI_HH__