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31 * Declaration of top level class for the Tsunami chipset. This class just
32 * retains pointers to all its children so the children can communicate.
35 #ifndef __TSUNAMI_HH__
36 #define __TSUNAMI_HH__
38 #include "dev/platform.hh"
50 * Top level class for Tsunami Chipset emulation.
51 * This structure just contains pointers to all the
52 * children so the children can commnicate to do the
56 class Tsunami : public Platform
60 /** Max number of CPUs in a Tsunami */
61 static const int Max_CPUs = 4;
63 /** Pointer to the system */
66 /** Pointer to the TsunamiIO device which has the RTC */
69 /** Pointer to the Tsunami CChip.
70 * The chip contains some configuration information and
71 * all the interrupt mask and status registers
75 /** Pointer to the Tsunami PChip.
76 * The pchip is the interface to the PCI bus, in our case
77 * it does not have to do much.
81 int intr_sum_type[Tsunami::Max_CPUs];
82 int ipi_pending[Tsunami::Max_CPUs];
86 * Constructor for the Tsunami Class.
87 * @param name name of the object
88 * @param con pointer to the console
89 * @param intrcontrol pointer to the interrupt controller
90 * @param intrFreq frequency that interrupts happen
92 Tsunami(const std::string &name, System *s, IntrControl *intctrl,
93 PciConfigAll *pci, int intrFreq);
96 * Return the interrupting frequency to AlphaAccess
97 * @return frequency of RTC interrupts
99 virtual Tick intrFrequency();
102 * Cause the cpu to post a serial interrupt to the CPU.
104 virtual void postConsoleInt();
107 * Clear a posted CPU interrupt (id=55)
109 virtual void clearConsoleInt();
112 * Serialize this object to the given output stream.
113 * @param os The stream to serialize to.
115 virtual void serialize(std::ostream &os);
118 * Reconstruct the state of this object from a checkpoint.
119 * @param cp The checkpoint use.
120 * @param section The section name of this object
122 virtual void unserialize(Checkpoint *cp, const std::string §ion);
125 #endif // __TSUNAMI_HH__