dev/tsunami.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /**
  30  * @file
  31  * Declaration of top level class for the Tsunami chipset. This class just
  32  * retains pointers to all its children so the children can communicate.
  33  */
  34
  35 #ifndef __DEV_TSUNAMI_HH__
  36 #define __DEV_TSUNAMI_HH__
  37
  38 #include "dev/platform.hh"
  39
  40 class IdeController;
  41 class TsunamiCChip;
  42 class TsunamiPChip;
  43 class TsunamiIO;
  44 class System;
  45
  46 /**
  47   * Top level class for Tsunami Chipset emulation.
  48   * This structure just contains pointers to all the
  49   * children so the children can commnicate to do the
  50   * read work
  51   */
  52
  53 class Tsunami : public Platform
  54 {
  55   public:
  56     /** Max number of CPUs in a Tsunami */
  57     static const int Max_CPUs = 64;
  58
  59     /** Pointer to the system */
  60     System *system;
  61
  62     /** Pointer to the TsunamiIO device which has the RTC */
  63     TsunamiIO *io;
  64
  65     /** Pointer to the Tsunami CChip.
  66      * The chip contains some configuration information and
  67      * all the interrupt mask and status registers
  68      */
  69     TsunamiCChip *cchip;
  70
  71     /** Pointer to the Tsunami PChip.
  72      * The pchip is the interface to the PCI bus, in our case
  73      * it does not have to do much.
  74      */
  75     TsunamiPChip *pchip;
  76
  77     int intr_sum_type[Tsunami::Max_CPUs];
  78     int ipi_pending[Tsunami::Max_CPUs];
  79
  80   public:
  81     /**
  82      * Constructor for the Tsunami Class.
  83      * @param name name of the object
  84      * @param intrctrl pointer to the interrupt controller
  85      */
  86     Tsunami(const std::string &name, System *s, IntrControl *intctrl);
  87
  88     /**
  89      * Return the interrupting frequency to AlphaAccess
  90      * @return frequency of RTC interrupts
  91      */
  92     virtual Tick intrFrequency();
  93
  94     /**
  95      * Cause the cpu to post a serial interrupt to the CPU.
  96      */
  97     virtual void postConsoleInt();
  98
  99     /**
 100      * Clear a posted CPU interrupt (id=55)
 101      */
 102     virtual void clearConsoleInt();
 103
 104     /**
 105      * Cause the chipset to post a cpi interrupt to the CPU.
 106      */
 107     virtual void postPciInt(int line);
 108
 109     /**
 110      * Clear a posted PCI->CPU interrupt
 111      */
 112     virtual void clearPciInt(int line);
 113
 114     virtual Addr pciToDma(Addr pciAddr) const;
 115
 116     /**
 117      * Serialize this object to the given output stream.
 118      * @param os The stream to serialize to.
 119      */
 120     virtual void serialize(std::ostream &os);
 121
 122     /**
 123      * Reconstruct the state of this object from a checkpoint.
 124      * @param cp The checkpoint use.
 125      * @param section The section name of this object
 126      */
 127     virtual void unserialize(Checkpoint *cp, const std::string &section);
 128 };
 129
 130 #endif // __DEV_TSUNAMI_HH__