2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * Declaration of top level class for the Tsunami chipset. This class just
32 * retains pointers to all its children so the children can communicate.
35 #ifndef __TSUNAMI_HH__
36 #define __TSUNAMI_HH__
38 #include "dev/platform.hh"
50 * Top level class for Tsunami Chipset emulation.
51 * This structure just contains pointers to all the
52 * children so the children can commnicate to do the
56 class Tsunami : public Platform
60 /** Max number of CPUs in a Tsunami */
61 static const int Max_CPUs = 4;
63 /** Pointer to the system */
65 /** Pointer to the TsunamiIO device which has the RTC */
67 /** Pointer to the disk controller device */
68 IdeController *disk_controller;
69 /** Pointer to the ethernet controller device */
72 /** Pointer to the Tsunami CChip.
73 * The chip contains some configuration information and
74 * all the interrupt mask and status registers
78 /** Pointer to the Tsunami PChip.
79 * The pchip is the interface to the PCI bus, in our case
80 * it does not have to do much.
84 int intr_sum_type[Tsunami::Max_CPUs];
85 int ipi_pending[Tsunami::Max_CPUs];
89 * Constructor for the Tsunami Class.
90 * @param name name of the object
91 * @param con pointer to the console
92 * @param intrcontrol pointer to the interrupt controller
93 * @param intrFreq frequency that interrupts happen
95 Tsunami(const std::string &name, System *s, IntrControl *intctrl,
96 PciConfigAll *pci, int intrFreq);
99 * Return the interrupting frequency to AlphaAccess
100 * @return frequency of RTC interrupts
102 virtual Tick intrFrequency();
105 * Cause the cpu to post a serial interrupt to the CPU.
107 virtual void postConsoleInt();
110 * Clear a posted CPU interrupt (id=55)
112 virtual void clearConsoleInt();
115 * Serialize this object to the given output stream.
116 * @param os The stream to serialize to.
118 virtual void serialize(std::ostream &os);
121 * Reconstruct the state of this object from a checkpoint.
122 * @param cp The checkpoint use.
123 * @param section The section name of this object
125 virtual void unserialize(Checkpoint *cp, const std::string §ion);
128 #endif // __TSUNAMI_HH__