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31 * Declaration of top level class for the Tsunami chipset. This class just retains pointers
32 * to all its children so the children can communicate
35 #ifndef __TSUNAMI_HH__
36 #define __TSUNAMI_HH__
38 #include "sim/sim_object.hh"
41 class ConsoleListener;
43 class AdaptecController;
48 class TsunamiPCIConfig;
51 * Top level class for Tsunami Chipset emulation.
52 * This structure just contains pointers to all the
53 * children so the children can commnicate to do the
57 class Tsunami : public SimObject
61 /** Max number of CPUs in a Tsunami */
62 static const int Max_CPUs = 4;
64 /** Pointer to the interrupt controller (used to post and ack interrupts on the CPU) */
65 IntrControl *intrctrl;
66 /** Pointer to the UART emulation code */
69 /** Pointer to the SCSI controller device */
70 AdaptecController *scsi;
71 /** Pointer to the ethernet controller device */
74 /** Pointer to the Tsunami CChip.
75 * The chip contains some configuration information and
76 * all the interrupt mask and status registers
80 /** Pointer to the Tsunami PChip.
81 * The pchip is the interface to the PCI bus, in our case
82 * it does not have to do much.
86 /** Pointer to the Tsunami PCI Config Space
87 * The config space in tsunami all needs to return
88 * -1 if a device is not there.
90 TsunamiPCIConfig *pciconfig;
92 int intr_sum_type[Tsunami::Max_CPUs];
93 int ipi_pending[Tsunami::Max_CPUs];
95 int interrupt_frequency;
99 * Constructor for the Tsunami Class.
102 Tsunami(const std::string &name, AdaptecController *scsi,
104 SimConsole *, IntrControl *intctrl, int intrFreq);
106 virtual void serialize(std::ostream &os);
107 virtual void unserialize(Checkpoint *cp, const std::string §ion);
110 #endif // __TSUNAMI_HH__