Merge
[gem5.git] / dev / tsunami.hh
1 /*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /**
30 * @file
31 * Declaration of top level class for the Tsunami chipset. This class just
32 * retains pointers to all its children so the children can communicate.
33 */
34
35 #ifndef __TSUNAMI_HH__
36 #define __TSUNAMI_HH__
37
38 #include "dev/platform.hh"
39
40 class AdaptecController;
41 class TlaserClock;
42 class EtherDev;
43 class TsunamiCChip;
44 class TsunamiPChip;
45 class TsunamiIO;
46 class PCIConfigAll;
47 class System;
48
49 /**
50 * Top level class for Tsunami Chipset emulation.
51 * This structure just contains pointers to all the
52 * children so the children can commnicate to do the
53 * read work
54 */
55
56 class Tsunami : public Platform
57 {
58 public:
59
60 /** Max number of CPUs in a Tsunami */
61 static const int Max_CPUs = 4;
62
63 /** Pointer to the system */
64 System *system;
65 /** Pointer to the TsunamiIO device which has the RTC */
66 TsunamiIO *io;
67 /** Pointer to the SCSI controller device */
68 AdaptecController *scsi;
69 /** Pointer to the ethernet controller device */
70 EtherDev *ethernet;
71
72 /** Pointer to the Tsunami CChip.
73 * The chip contains some configuration information and
74 * all the interrupt mask and status registers
75 */
76 TsunamiCChip *cchip;
77
78 /** Pointer to the Tsunami PChip.
79 * The pchip is the interface to the PCI bus, in our case
80 * it does not have to do much.
81 */
82 TsunamiPChip *pchip;
83
84 /** Pointer to the PCI Config Space
85 * The config space in Tsunami all needs to return
86 * -1 if a device is not there.
87 */
88 PCIConfigAll *pciconfig;
89
90 int intr_sum_type[Tsunami::Max_CPUs];
91 int ipi_pending[Tsunami::Max_CPUs];
92
93 public:
94 /**
95 * Constructor for the Tsunami Class.
96 * @param name name of the object
97 * @param con pointer to the console
98 * @param intrcontrol pointer to the interrupt controller
99 * @param intrFreq frequency that interrupts happen
100 */
101 Tsunami(const std::string &name, System *s, SimConsole *con,
102 IntrControl *intctrl, int intrFreq);
103
104 virtual void serialize(std::ostream &os);
105 virtual void unserialize(Checkpoint *cp, const std::string &section);
106 };
107
108 #endif // __TSUNAMI_HH__