374c50d6614a0093ab696e8fa172202315075c48
4 * Emulation of the Tsunami CChip CSRs
11 #include "base/trace.hh"
12 #include "cpu/exec_context.hh"
13 #include "dev/console.hh"
14 #include "dev/tsunami_cchip.hh"
15 #include "dev/tsunamireg.h"
16 #include "dev/tsunami.hh"
17 #include "cpu/intr_control.hh"
18 #include "mem/functional_mem/memory_control.hh"
19 #include "sim/builder.hh"
20 #include "sim/system.hh"
24 TsunamiCChip::TsunamiCChip(const string
&name
, Tsunami
*t
, Addr a
,
25 MemoryController
*mmu
)
26 : FunctionalMemory(name
), addr(a
), tsunami(t
)
28 mmu
->add_child(this, Range
<Addr
>(addr
, addr
+ size
));
30 for(int i
=0; i
< Tsunami::Max_CPUs
; i
++) {
33 dirInterrupting
[i
] = false;
38 RTCInterrupting
= false;
40 //Put back pointer in tsunami
41 tsunami
->cchip
= this;
45 TsunamiCChip::read(MemReqPtr
&req
, uint8_t *data
)
47 DPRINTF(Tsunami
, "read va=%#x size=%d\n",
48 req
->vaddr
, req
->size
);
50 Addr daddr
= (req
->paddr
& size
) >> 6;
51 ExecContext
*xc
= req
->xc
;
55 case sizeof(uint64_t):
58 *(uint64_t*)data
= 0x0;
61 panic("TSDEV_CC_MTR not implemeted\n");
64 *(uint64_t*)data
= misc
| (xc
->cpu_id
& 0x3);
70 panic("TSDEV_CC_AARx not implemeted\n");
73 *(uint64_t*)data
= dim
[0];
76 *(uint64_t*)data
= dim
[1];
79 *(uint64_t*)data
= dim
[2];
82 *(uint64_t*)data
= dim
[3];
85 *(uint64_t*)data
= dir
[0];
88 *(uint64_t*)data
= dir
[1];
91 *(uint64_t*)data
= dir
[2];
94 *(uint64_t*)data
= dir
[3];
97 *(uint64_t*)data
= drir
;
100 panic("TSDEV_CC_PRBEN not implemented\n");
106 panic("TSDEV_CC_IICx not implemented\n");
112 panic("TSDEV_CC_MPRx not implemented\n");
115 panic("default in cchip read reached, accessing 0x%x\n");
119 case sizeof(uint32_t):
120 case sizeof(uint16_t):
121 case sizeof(uint8_t):
123 panic("invalid access size(?) for tsunami register!\n");
125 DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr
, req
->size
);
131 TsunamiCChip::write(MemReqPtr
&req
, const uint8_t *data
)
133 DPRINTF(Tsunami
, "write - va=%#x size=%d \n",
134 req
->vaddr
, req
->size
);
136 Addr daddr
= (req
->paddr
& size
) >> 6;
140 case sizeof(uint64_t):
143 panic("TSDEV_CC_CSR write\n");
146 panic("TSDEV_CC_MTR write not implemented\n");
149 //If it is the seventh bit, clear the RTC interrupt
150 if ((*(uint64_t*) data
) & (1<<4)) {
151 RTCInterrupting
= false;
152 tsunami
->intrctrl
->clear(0, TheISA::INTLEVEL_IRQ2
, 0);
153 DPRINTF(Tsunami
, "clearing rtc interrupt\n");
155 } else panic("TSDEV_CC_MISC write not implemented\n");
161 panic("TSDEV_CC_AARx write not implemeted\n");
164 dim
[0] = *(uint64_t*)data
;
166 dir
[0] = dim
[0] & drir
;
167 if (!dirInterrupting
[0]) {
168 dirInterrupting
[0] = true;
169 tsunami
->intrctrl
->post(0, TheISA::INTLEVEL_IRQ1
, 0);
170 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
175 dim
[1] = *(uint64_t*)data
;
177 dir
[1] = dim
[1] & drir
;
178 if (!dirInterrupting
[1]) {
179 dirInterrupting
[1] = true;
180 tsunami
->intrctrl
->post(1, TheISA::INTLEVEL_IRQ1
, 0);
181 DPRINTF(Tsunami
, "posting dir interrupt to cpu 1\n");
186 dim
[2] = *(uint64_t*)data
;
188 dir
[2] = dim
[2] & drir
;
189 if (!dirInterrupting
[2]) {
190 dirInterrupting
[2] = true;
191 tsunami
->intrctrl
->post(2, TheISA::INTLEVEL_IRQ1
, 0);
192 DPRINTF(Tsunami
, "posting dir interrupt to cpu 2\n");
197 dim
[3] = *(uint64_t*)data
;
198 if ((dim
[3] & drir
) /*And Not Already Int*/) {
199 dir
[3] = dim
[3] & drir
;
200 if (!dirInterrupting
[3]) {
201 dirInterrupting
[3] = true;
202 tsunami
->intrctrl
->post(3, TheISA::INTLEVEL_IRQ1
, 0);
203 DPRINTF(Tsunami
, "posting dir interrupt to cpu 3\n");
211 panic("TSDEV_CC_DIR write not implemented\n");
214 panic("TSDEV_CC_DRIR write not implemented\n");
217 panic("TSDEV_CC_PRBEN write not implemented\n");
223 panic("TSDEV_CC_IICx write not implemented\n");
229 panic("TSDEV_CC_MPRx write not implemented\n");
232 panic("default in cchip read reached, accessing 0x%x\n");
236 case sizeof(uint32_t):
237 case sizeof(uint16_t):
238 case sizeof(uint8_t):
240 panic("invalid access size(?) for tsunami register!\n");
243 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr
, req
->size
);
249 TsunamiCChip::postDRIR(uint64_t bitvector
)
252 for(int i
=0; i
< Tsunami::Max_CPUs
; i
++) {
253 if (bitvector
& dim
[i
]) {
255 if (!dirInterrupting
[i
]) {
256 dirInterrupting
[i
] = true;
257 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, 0);
258 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d\n",i
);
265 TsunamiCChip::clearDRIR(uint64_t bitvector
)
268 for(int i
=0; i
< Tsunami::Max_CPUs
; i
++) {
269 dir
[i
] &= ~bitvector
;
271 dirInterrupting
[i
] = false;
272 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, 0);
273 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d\n", i
);
280 TsunamiCChip::serialize(std::ostream
&os
)
282 // code should be written
286 TsunamiCChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
288 //code should be written
291 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
293 SimObjectParam
<Tsunami
*> tsunami
;
294 SimObjectParam
<MemoryController
*> mmu
;
297 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
299 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
301 INIT_PARAM(tsunami
, "Tsunami"),
302 INIT_PARAM(mmu
, "Memory Controller"),
303 INIT_PARAM(addr
, "Device Address")
305 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
307 CREATE_SIM_OBJECT(TsunamiCChip
)
309 return new TsunamiCChip(getInstanceName(), tsunami
, addr
, mmu
);
312 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip
)