dev/tsunami_cchip.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Emulation of the Tsunami CChip CSRs
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "base/trace.hh"
  38 #include "dev/tsunami_cchip.hh"
  39 #include "dev/tsunamireg.h"
  40 #include "dev/tsunami.hh"
  41 #include "mem/bus/bus.hh"
  42 #include "mem/bus/pio_interface.hh"
  43 #include "mem/bus/pio_interface_impl.hh"
  44 #include "mem/functional/memory_control.hh"
  45 #include "cpu/intr_control.hh"
  46 #include "sim/builder.hh"
  47 #include "sim/system.hh"
  48
  49 using namespace std;
  50 //Should this be AlphaISA?
  51 using namespace TheISA;
  52
  53 TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
  54                            MemoryController *mmu, HierParams *hier,
  55                            Bus* pio_bus, Tick pio_latency)
  56     : PioDevice(name, t), addr(a), tsunami(t)
  57 {
  58     mmu->add_child(this, RangeSize(addr, size));
  59
  60     if (pio_bus) {
  61         pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
  62                                       &TsunamiCChip::cacheAccess);
  63         pioInterface->addAddrRange(RangeSize(addr, size));
  64         pioLatency = pio_latency * pio_bus->clockRate;
  65     }
  66
  67     drir = 0;
  68     ipint = 0;
  69     itint = 0;
  70
  71     for (int x = 0; x < Tsunami::Max_CPUs; x++)
  72     {
  73         dim[x] = 0;
  74         dir[x] = 0;
  75     }
  76
  77     //Put back pointer in tsunami
  78     tsunami->cchip = this;
  79 }
  80
  81 Fault
  82 TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
  83 {
  84     DPRINTF(Tsunami, "read  va=%#x size=%d\n", req->vaddr, req->size);
  85
  86     Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
  87     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
  88
  89     ExecContext *xc = req->xc;
  90
  91     switch (req->size) {
  92
  93       case sizeof(uint64_t):
  94           if (daddr & TSDEV_CC_BDIMS)
  95           {
  96               *(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
  97               return NoFault;
  98           }
  99
 100           if (daddr & TSDEV_CC_BDIRS)
 101           {
 102               *(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
 103               return NoFault;
 104           }
 105
 106           switch(regnum) {
 107               case TSDEV_CC_CSR:
 108                   *(uint64_t*)data = 0x0;
 109                   return NoFault;
 110               case TSDEV_CC_MTR:
 111                   panic("TSDEV_CC_MTR not implemeted\n");
 112                    return NoFault;
 113               case TSDEV_CC_MISC:
 114                   *(uint64_t*)data = (ipint << 8) & 0xF |
 115                                      (itint << 4) & 0xF |
 116                                      (xc->cpu_id & 0x3);
 117                   return NoFault;
 118               case TSDEV_CC_AAR0:
 119               case TSDEV_CC_AAR1:
 120               case TSDEV_CC_AAR2:
 121               case TSDEV_CC_AAR3:
 122                   *(uint64_t*)data = 0;
 123                   return NoFault;
 124               case TSDEV_CC_DIM0:
 125                   *(uint64_t*)data = dim[0];
 126                   return NoFault;
 127               case TSDEV_CC_DIM1:
 128                   *(uint64_t*)data = dim[1];
 129                   return NoFault;
 130               case TSDEV_CC_DIM2:
 131                   *(uint64_t*)data = dim[2];
 132                   return NoFault;
 133               case TSDEV_CC_DIM3:
 134                   *(uint64_t*)data = dim[3];
 135                   return NoFault;
 136               case TSDEV_CC_DIR0:
 137                   *(uint64_t*)data = dir[0];
 138                   return NoFault;
 139               case TSDEV_CC_DIR1:
 140                   *(uint64_t*)data = dir[1];
 141                   return NoFault;
 142               case TSDEV_CC_DIR2:
 143                   *(uint64_t*)data = dir[2];
 144                   return NoFault;
 145               case TSDEV_CC_DIR3:
 146                   *(uint64_t*)data = dir[3];
 147                   return NoFault;
 148               case TSDEV_CC_DRIR:
 149                   *(uint64_t*)data = drir;
 150                   return NoFault;
 151               case TSDEV_CC_PRBEN:
 152                   panic("TSDEV_CC_PRBEN not implemented\n");
 153                   return NoFault;
 154               case TSDEV_CC_IIC0:
 155               case TSDEV_CC_IIC1:
 156               case TSDEV_CC_IIC2:
 157               case TSDEV_CC_IIC3:
 158                   panic("TSDEV_CC_IICx not implemented\n");
 159                   return NoFault;
 160               case TSDEV_CC_MPR0:
 161               case TSDEV_CC_MPR1:
 162               case TSDEV_CC_MPR2:
 163               case TSDEV_CC_MPR3:
 164                   panic("TSDEV_CC_MPRx not implemented\n");
 165                   return NoFault;
 166               case TSDEV_CC_IPIR:
 167                   *(uint64_t*)data = ipint;
 168                   return NoFault;
 169               case TSDEV_CC_ITIR:
 170                   *(uint64_t*)data = itint;
 171                   return NoFault;
 172               default:
 173                   panic("default in cchip read reached, accessing 0x%x\n");
 174            } // uint64_t
 175
 176       break;
 177       case sizeof(uint32_t):
 178           if (regnum == TSDEV_CC_DRIR) {
 179               warn("accessing DRIR with 32 bit read, "
 180                    "hopefully your just reading this for timing");
 181               *(uint32_t*)data = drir;
 182           } else
 183               panic("invalid access size(?) for tsunami register!\n");
 184           return NoFault;
 185       case sizeof(uint16_t):
 186       case sizeof(uint8_t):
 187       default:
 188         panic("invalid access size(?) for tsunami register!\n");
 189     }
 190     DPRINTFN("Tsunami CChip ERROR: read  regnum=%#x size=%d\n", regnum, req->size);
 191
 192     return NoFault;
 193 }
 194
 195 Fault
 196 TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
 197 {
 198     DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
 199             req->vaddr, *(uint64_t*)data, req->size);
 200
 201     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 202     Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
 203
 204     bool supportedWrite = false;
 205
 206     switch (req->size) {
 207
 208       case sizeof(uint64_t):
 209           if (daddr & TSDEV_CC_BDIMS)
 210           {
 211               int number = (daddr >> 4) & 0x3F;
 212
 213               uint64_t bitvector;
 214               uint64_t olddim;
 215               uint64_t olddir;
 216
 217               olddim = dim[number];
 218               olddir = dir[number];
 219               dim[number] = *(uint64_t*)data;
 220               dir[number] = dim[number] & drir;
 221               for(int x = 0; x < Tsunami::Max_CPUs; x++)
 222               {
 223                   bitvector = ULL(1) << x;
 224                   // Figure out which bits have changed
 225                   if ((dim[number] & bitvector) != (olddim & bitvector))
 226                   {
 227                       // The bit is now set and it wasn't before (set)
 228                       if((dim[number] & bitvector) && (dir[number] & bitvector))
 229                       {
 230                           tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 231                           DPRINTF(Tsunami, "dim write resulting in posting dir"
 232                                   " interrupt to cpu %d\n", number);
 233                       }
 234                       else if ((olddir & bitvector) &&
 235                               !(dir[number] & bitvector))
 236                       {
 237                           // The bit was set and now its now clear and
 238                           // we were interrupting on that bit before
 239                           tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 240                           DPRINTF(Tsunami, "dim write resulting in clear"
 241                                   " dir interrupt to cpu %d\n", number);
 242
 243                       }
 244
 245
 246                   }
 247               }
 248               return NoFault;
 249           }
 250
 251           switch(regnum) {
 252               case TSDEV_CC_CSR:
 253                   panic("TSDEV_CC_CSR write\n");
 254                   return NoFault;
 255               case TSDEV_CC_MTR:
 256                   panic("TSDEV_CC_MTR write not implemented\n");
 257                    return NoFault;
 258               case TSDEV_CC_MISC:
 259                 uint64_t ipreq;
 260                 ipreq = (*(uint64_t*)data >> 12) & 0xF;
 261                 //If it is bit 12-15, this is an IPI post
 262                 if (ipreq) {
 263                     reqIPI(ipreq);
 264                     supportedWrite = true;
 265                 }
 266
 267                 //If it is bit 8-11, this is an IPI clear
 268                 uint64_t ipintr;
 269                 ipintr = (*(uint64_t*)data >> 8) & 0xF;
 270                 if (ipintr) {
 271                     clearIPI(ipintr);
 272                     supportedWrite = true;
 273                 }
 274
 275                 //If it is the 4-7th bit, clear the RTC interrupt
 276                 uint64_t itintr;
 277                 itintr = (*(uint64_t*)data >> 4) & 0xF;
 278                 if (itintr) {
 279                     clearITI(itintr);
 280                     supportedWrite = true;
 281                 }
 282
 283                 // ignore NXMs
 284                 if (*(uint64_t*)data & 0x10000000)
 285                     supportedWrite = true;
 286
 287                 if(!supportedWrite)
 288                     panic("TSDEV_CC_MISC write not implemented\n");
 289
 290                 return NoFault;
 291               case TSDEV_CC_AAR0:
 292               case TSDEV_CC_AAR1:
 293               case TSDEV_CC_AAR2:
 294               case TSDEV_CC_AAR3:
 295                   panic("TSDEV_CC_AARx write not implemeted\n");
 296                   return NoFault;
 297               case TSDEV_CC_DIM0:
 298               case TSDEV_CC_DIM1:
 299               case TSDEV_CC_DIM2:
 300               case TSDEV_CC_DIM3:
 301                   int number;
 302                   if(regnum == TSDEV_CC_DIM0)
 303                       number = 0;
 304                   else if(regnum == TSDEV_CC_DIM1)
 305                       number = 1;
 306                   else if(regnum == TSDEV_CC_DIM2)
 307                       number = 2;
 308                   else
 309                       number = 3;
 310
 311                   uint64_t bitvector;
 312                   uint64_t olddim;
 313                   uint64_t olddir;
 314
 315                   olddim = dim[number];
 316                   olddir = dir[number];
 317                   dim[number] = *(uint64_t*)data;
 318                   dir[number] = dim[number] & drir;
 319                   for(int x = 0; x < 64; x++)
 320                   {
 321                       bitvector = ULL(1) << x;
 322                       // Figure out which bits have changed
 323                       if ((dim[number] & bitvector) != (olddim & bitvector))
 324                       {
 325                           // The bit is now set and it wasn't before (set)
 326                           if((dim[number] & bitvector) && (dir[number] & bitvector))
 327                           {
 328                               tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 329                               DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
 330                           }
 331                           else if ((olddir & bitvector) &&
 332                                   !(dir[number] & bitvector))
 333                           {
 334                               // The bit was set and now its now clear and
 335                               // we were interrupting on that bit before
 336                               tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 337                               DPRINTF(Tsunami, "dim write resulting in clear"
 338                                       " dir interrupt to cpu %d\n",
 339                                       x);
 340
 341                           }
 342
 343
 344                       }
 345                   }
 346                   return NoFault;
 347               case TSDEV_CC_DIR0:
 348               case TSDEV_CC_DIR1:
 349               case TSDEV_CC_DIR2:
 350               case TSDEV_CC_DIR3:
 351                   panic("TSDEV_CC_DIR write not implemented\n");
 352               case TSDEV_CC_DRIR:
 353                   panic("TSDEV_CC_DRIR write not implemented\n");
 354               case TSDEV_CC_PRBEN:
 355                   panic("TSDEV_CC_PRBEN write not implemented\n");
 356               case TSDEV_CC_IIC0:
 357               case TSDEV_CC_IIC1:
 358               case TSDEV_CC_IIC2:
 359               case TSDEV_CC_IIC3:
 360                   panic("TSDEV_CC_IICx write not implemented\n");
 361               case TSDEV_CC_MPR0:
 362               case TSDEV_CC_MPR1:
 363               case TSDEV_CC_MPR2:
 364               case TSDEV_CC_MPR3:
 365                   panic("TSDEV_CC_MPRx write not implemented\n");
 366               case TSDEV_CC_IPIR:
 367                   clearIPI(*(uint64_t*)data);
 368                   return NoFault;
 369               case TSDEV_CC_ITIR:
 370                   clearITI(*(uint64_t*)data);
 371                   return NoFault;
 372               case TSDEV_CC_IPIQ:
 373                   reqIPI(*(uint64_t*)data);
 374                   return NoFault;
 375               default:
 376                   panic("default in cchip read reached, accessing 0x%x\n");
 377           }
 378
 379       break;
 380       case sizeof(uint32_t):
 381       case sizeof(uint16_t):
 382       case sizeof(uint8_t):
 383       default:
 384         panic("invalid access size(?) for tsunami register!\n");
 385     }
 386
 387     DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
 388
 389     return NoFault;
 390 }
 391
 392 void
 393 TsunamiCChip::clearIPI(uint64_t ipintr)
 394 {
 395     int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
 396     assert(numcpus <= Tsunami::Max_CPUs);
 397
 398     if (ipintr) {
 399         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 400             // Check each cpu bit
 401             uint64_t cpumask = ULL(1) << cpunum;
 402             if (ipintr & cpumask) {
 403                 // Check if there is a pending ipi
 404                 if (ipint & cpumask) {
 405                     ipint &= ~cpumask;
 406                     tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 407                     DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
 408                 }
 409                 else
 410                     warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
 411             }
 412         }
 413     }
 414     else
 415         panic("Big IPI Clear, but not processors indicated\n");
 416 }
 417
 418 void
 419 TsunamiCChip::clearITI(uint64_t itintr)
 420 {
 421     int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
 422     assert(numcpus <= Tsunami::Max_CPUs);
 423
 424     if (itintr) {
 425         for (int i=0; i < numcpus; i++) {
 426             uint64_t cpumask = ULL(1) << i;
 427             if (itintr & cpumask & itint) {
 428                 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
 429                 itint &= ~cpumask;
 430                 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
 431             }
 432         }
 433     }
 434     else
 435         panic("Big ITI Clear, but not processors indicated\n");
 436 }
 437
 438 void
 439 TsunamiCChip::reqIPI(uint64_t ipreq)
 440 {
 441     int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
 442     assert(numcpus <= Tsunami::Max_CPUs);
 443
 444     if (ipreq) {
 445         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 446             // Check each cpu bit
 447             uint64_t cpumask = ULL(1) << cpunum;
 448             if (ipreq & cpumask) {
 449                 // Check if there is already an ipi (bits 8:11)
 450                 if (!(ipint & cpumask)) {
 451                     ipint  |= cpumask;
 452                     tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 453                     DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
 454                 }
 455                 else
 456                     warn("post IPI for CPU=%d, but IPI already\n", cpunum);
 457             }
 458         }
 459     }
 460     else
 461         panic("Big IPI Request, but not processors indicated\n");
 462 }
 463
 464
 465 void
 466 TsunamiCChip::postRTC()
 467 {
 468     int size = tsunami->intrctrl->cpu->system->execContexts.size();
 469     assert(size <= Tsunami::Max_CPUs);
 470
 471     for (int i = 0; i < size; i++) {
 472         uint64_t cpumask = ULL(1) << i;
 473         if (!(cpumask & itint)) {
 474             itint |= cpumask;
 475             tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
 476             DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
 477         }
 478     }
 479
 480 }
 481
 482 void
 483 TsunamiCChip::postDRIR(uint32_t interrupt)
 484 {
 485     uint64_t bitvector = ULL(1) << interrupt;
 486     uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
 487     assert(size <= Tsunami::Max_CPUs);
 488     drir |= bitvector;
 489
 490     for(int i=0; i < size; i++) {
 491         dir[i] = dim[i] & drir;
 492         if (dim[i] & bitvector) {
 493                 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
 494                 DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
 495                         "interrupt %d\n",i, interrupt);
 496         }
 497     }
 498 }
 499
 500 void
 501 TsunamiCChip::clearDRIR(uint32_t interrupt)
 502 {
 503     uint64_t bitvector = ULL(1) << interrupt;
 504     uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
 505     assert(size <= Tsunami::Max_CPUs);
 506
 507     if (drir & bitvector)
 508     {
 509         drir &= ~bitvector;
 510         for(int i=0; i < size; i++) {
 511             if (dir[i] & bitvector) {
 512                 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
 513                 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
 514                     "interrupt %d\n",i, interrupt);
 515
 516             }
 517             dir[i] = dim[i] & drir;
 518         }
 519     }
 520     else
 521         DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
 522 }
 523
 524 Tick
 525 TsunamiCChip::cacheAccess(MemReqPtr &req)
 526 {
 527     return curTick + pioLatency;
 528 }
 529
 530
 531 void
 532 TsunamiCChip::serialize(std::ostream &os)
 533 {
 534     SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 535     SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 536     SERIALIZE_SCALAR(ipint);
 537     SERIALIZE_SCALAR(itint);
 538     SERIALIZE_SCALAR(drir);
 539 }
 540
 541 void
 542 TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
 543 {
 544     UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 545     UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 546     UNSERIALIZE_SCALAR(ipint);
 547     UNSERIALIZE_SCALAR(itint);
 548     UNSERIALIZE_SCALAR(drir);
 549 }
 550
 551 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 552
 553     SimObjectParam<Tsunami *> tsunami;
 554     SimObjectParam<MemoryController *> mmu;
 555     Param<Addr> addr;
 556     SimObjectParam<Bus*> pio_bus;
 557     Param<Tick> pio_latency;
 558     SimObjectParam<HierParams *> hier;
 559
 560 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 561
 562 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 563
 564     INIT_PARAM(tsunami, "Tsunami"),
 565     INIT_PARAM(mmu, "Memory Controller"),
 566     INIT_PARAM(addr, "Device Address"),
 567     INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
 568     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 569     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 570
 571 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 572
 573 CREATE_SIM_OBJECT(TsunamiCChip)
 574 {
 575     return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier,
 576                             pio_bus, pio_latency);
 577 }
 578
 579 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)