dev/tsunami_cchip.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Emulation of the Tsunami CChip CSRs
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "arch/alpha/ev5.hh"
  38 #include "base/trace.hh"
  39 #include "dev/tsunami_cchip.hh"
  40 #include "dev/tsunamireg.h"
  41 #include "dev/tsunami.hh"
  42 #include "mem/port.hh"
  43 #include "cpu/exec_context.hh"
  44 #include "cpu/intr_control.hh"
  45 #include "sim/builder.hh"
  46 #include "sim/system.hh"
  47
  48 using namespace std;
  49 //Should this be AlphaISA?
  50 using namespace TheISA;
  51
  52 TsunamiCChip::TsunamiCChip(Params *p)
  53     : BasicPioDevice(p), tsunami(p->tsunami)
  54 {
  55     pioSize = 0xfffffff;
  56
  57     drir = 0;
  58     ipint = 0;
  59     itint = 0;
  60
  61     for (int x = 0; x < Tsunami::Max_CPUs; x++)
  62     {
  63         dim[x] = 0;
  64         dir[x] = 0;
  65     }
  66
  67     //Put back pointer in tsunami
  68     tsunami->cchip = this;
  69 }
  70
  71 Tick
  72 TsunamiCChip::read(Packet &pkt)
  73 {
  74     DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt.addr, pkt.size);
  75
  76     assert(pkt.result == Unknown);
  77     assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
  78
  79     pkt.time = curTick + pioDelay;
  80     Addr regnum = (pkt.addr - pioAddr) >> 6;
  81     Addr daddr = (pkt.addr - pioAddr);
  82
  83     uint64_t *data64;
  84
  85     switch (pkt.size) {
  86
  87       case sizeof(uint64_t):
  88           if (!pkt.data) {
  89               data64 = new uint64_t;
  90               pkt.data = (uint8_t*)data64;
  91           } else
  92               data64 = (uint64_t*)pkt.data;
  93
  94           if (daddr & TSDEV_CC_BDIMS)
  95           {
  96               *data64 = dim[(daddr >> 4) & 0x3F];
  97               break;
  98           }
  99
 100           if (daddr & TSDEV_CC_BDIRS)
 101           {
 102               *data64 = dir[(daddr >> 4) & 0x3F];
 103               break;
 104           }
 105
 106           switch(regnum) {
 107               case TSDEV_CC_CSR:
 108                   *data64 = 0x0;
 109                   break;
 110               case TSDEV_CC_MTR:
 111                   panic("TSDEV_CC_MTR not implemeted\n");
 112                    break;
 113               case TSDEV_CC_MISC:
 114                   *data64 = (ipint << 8) & 0xF | (itint << 4) & 0xF |
 115                                      (pkt.req->getCpuNum() & 0x3);
 116                   break;
 117               case TSDEV_CC_AAR0:
 118               case TSDEV_CC_AAR1:
 119               case TSDEV_CC_AAR2:
 120               case TSDEV_CC_AAR3:
 121                   *data64 = 0;
 122                   break;
 123               case TSDEV_CC_DIM0:
 124                   *data64 = dim[0];
 125                   break;
 126               case TSDEV_CC_DIM1:
 127                   *data64 = dim[1];
 128                   break;
 129               case TSDEV_CC_DIM2:
 130                   *data64 = dim[2];
 131                   break;
 132               case TSDEV_CC_DIM3:
 133                   *data64 = dim[3];
 134                   break;
 135               case TSDEV_CC_DIR0:
 136                   *data64 = dir[0];
 137                   break;
 138               case TSDEV_CC_DIR1:
 139                   *data64 = dir[1];
 140                   break;
 141               case TSDEV_CC_DIR2:
 142                   *data64 = dir[2];
 143                   break;
 144               case TSDEV_CC_DIR3:
 145                   *data64 = dir[3];
 146                   break;
 147               case TSDEV_CC_DRIR:
 148                   *data64 = drir;
 149                   break;
 150               case TSDEV_CC_PRBEN:
 151                   panic("TSDEV_CC_PRBEN not implemented\n");
 152                   break;
 153               case TSDEV_CC_IIC0:
 154               case TSDEV_CC_IIC1:
 155               case TSDEV_CC_IIC2:
 156               case TSDEV_CC_IIC3:
 157                   panic("TSDEV_CC_IICx not implemented\n");
 158                   break;
 159               case TSDEV_CC_MPR0:
 160               case TSDEV_CC_MPR1:
 161               case TSDEV_CC_MPR2:
 162               case TSDEV_CC_MPR3:
 163                   panic("TSDEV_CC_MPRx not implemented\n");
 164                   break;
 165               case TSDEV_CC_IPIR:
 166                   *data64 = ipint;
 167                   break;
 168               case TSDEV_CC_ITIR:
 169                   *data64 = itint;
 170                   break;
 171               default:
 172                   panic("default in cchip read reached, accessing 0x%x\n");
 173            } // uint64_t
 174
 175       break;
 176       case sizeof(uint32_t):
 177       case sizeof(uint16_t):
 178       case sizeof(uint8_t):
 179       default:
 180         panic("invalid access size(?) for tsunami register!\n");
 181     }
 182     DPRINTF(Tsunami, "Tsunami CChip: read  regnum=%#x size=%d data=%lld\n",
 183             regnum, pkt.size, *data64);
 184
 185     pkt.result = Success;
 186     return pioDelay;
 187 }
 188
 189 Tick
 190 TsunamiCChip::write(Packet &pkt)
 191 {
 192     pkt.time = curTick + pioDelay;
 193
 194
 195     assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
 196     Addr daddr = pkt.addr - pioAddr;
 197     Addr regnum = (pkt.addr - pioAddr) >> 6 ;
 198
 199
 200     uint64_t val = *(uint64_t *)pkt.data;
 201     assert(pkt.size == sizeof(uint64_t));
 202
 203     DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt.addr, val);
 204
 205     bool supportedWrite = false;
 206
 207
 208     if (daddr & TSDEV_CC_BDIMS)
 209     {
 210         int number = (daddr >> 4) & 0x3F;
 211
 212         uint64_t bitvector;
 213         uint64_t olddim;
 214         uint64_t olddir;
 215
 216         olddim = dim[number];
 217         olddir = dir[number];
 218         dim[number] = val;
 219         dir[number] = dim[number] & drir;
 220         for(int x = 0; x < Tsunami::Max_CPUs; x++)
 221         {
 222             bitvector = ULL(1) << x;
 223             // Figure out which bits have changed
 224             if ((dim[number] & bitvector) != (olddim & bitvector))
 225             {
 226                 // The bit is now set and it wasn't before (set)
 227                 if((dim[number] & bitvector) && (dir[number] & bitvector))
 228                 {
 229                     tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 230                     DPRINTF(Tsunami, "dim write resulting in posting dir"
 231                             " interrupt to cpu %d\n", number);
 232                 }
 233                 else if ((olddir & bitvector) &&
 234                         !(dir[number] & bitvector))
 235                 {
 236                     // The bit was set and now its now clear and
 237                     // we were interrupting on that bit before
 238                     tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 239                     DPRINTF(Tsunami, "dim write resulting in clear"
 240                             " dir interrupt to cpu %d\n", number);
 241
 242                 }
 243
 244
 245             }
 246         }
 247     } else {
 248         switch(regnum) {
 249           case TSDEV_CC_CSR:
 250               panic("TSDEV_CC_CSR write\n");
 251           case TSDEV_CC_MTR:
 252               panic("TSDEV_CC_MTR write not implemented\n");
 253           case TSDEV_CC_MISC:
 254             uint64_t ipreq;
 255             ipreq = (val >> 12) & 0xF;
 256             //If it is bit 12-15, this is an IPI post
 257             if (ipreq) {
 258                 reqIPI(ipreq);
 259                 supportedWrite = true;
 260             }
 261
 262             //If it is bit 8-11, this is an IPI clear
 263             uint64_t ipintr;
 264             ipintr = (val >> 8) & 0xF;
 265             if (ipintr) {
 266                 clearIPI(ipintr);
 267                 supportedWrite = true;
 268             }
 269
 270             //If it is the 4-7th bit, clear the RTC interrupt
 271             uint64_t itintr;
 272               itintr = (val >> 4) & 0xF;
 273             if (itintr) {
 274                   clearITI(itintr);
 275                 supportedWrite = true;
 276             }
 277
 278               // ignore NXMs
 279               if (val & 0x10000000)
 280                   supportedWrite = true;
 281
 282             if(!supportedWrite)
 283                   panic("TSDEV_CC_MISC write not implemented\n");
 284
 285             break;
 286             case TSDEV_CC_AAR0:
 287             case TSDEV_CC_AAR1:
 288             case TSDEV_CC_AAR2:
 289             case TSDEV_CC_AAR3:
 290                 panic("TSDEV_CC_AARx write not implemeted\n");
 291             case TSDEV_CC_DIM0:
 292             case TSDEV_CC_DIM1:
 293             case TSDEV_CC_DIM2:
 294             case TSDEV_CC_DIM3:
 295                 int number;
 296                 if(regnum == TSDEV_CC_DIM0)
 297                     number = 0;
 298                 else if(regnum == TSDEV_CC_DIM1)
 299                     number = 1;
 300                 else if(regnum == TSDEV_CC_DIM2)
 301                     number = 2;
 302                 else
 303                     number = 3;
 304
 305                 uint64_t bitvector;
 306                 uint64_t olddim;
 307                 uint64_t olddir;
 308
 309                 olddim = dim[number];
 310                 olddir = dir[number];
 311                 dim[number] = val;
 312                 dir[number] = dim[number] & drir;
 313                 for(int x = 0; x < 64; x++)
 314                 {
 315                     bitvector = ULL(1) << x;
 316                     // Figure out which bits have changed
 317                     if ((dim[number] & bitvector) != (olddim & bitvector))
 318                     {
 319                         // The bit is now set and it wasn't before (set)
 320                         if((dim[number] & bitvector) && (dir[number] & bitvector))
 321                         {
 322                           tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 323                           DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
 324                         }
 325                         else if ((olddir & bitvector) &&
 326                                 !(dir[number] & bitvector))
 327                         {
 328                             // The bit was set and now its now clear and
 329                             // we were interrupting on that bit before
 330                             tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 331                           DPRINTF(Tsunami, "dim write resulting in clear"
 332                                     " dir interrupt to cpu %d\n",
 333                                     x);
 334
 335                         }
 336
 337
 338                     }
 339                 }
 340                 break;
 341             case TSDEV_CC_DIR0:
 342             case TSDEV_CC_DIR1:
 343             case TSDEV_CC_DIR2:
 344             case TSDEV_CC_DIR3:
 345                 panic("TSDEV_CC_DIR write not implemented\n");
 346             case TSDEV_CC_DRIR:
 347                 panic("TSDEV_CC_DRIR write not implemented\n");
 348             case TSDEV_CC_PRBEN:
 349                 panic("TSDEV_CC_PRBEN write not implemented\n");
 350             case TSDEV_CC_IIC0:
 351             case TSDEV_CC_IIC1:
 352             case TSDEV_CC_IIC2:
 353             case TSDEV_CC_IIC3:
 354                 panic("TSDEV_CC_IICx write not implemented\n");
 355             case TSDEV_CC_MPR0:
 356             case TSDEV_CC_MPR1:
 357             case TSDEV_CC_MPR2:
 358             case TSDEV_CC_MPR3:
 359                 panic("TSDEV_CC_MPRx write not implemented\n");
 360             case TSDEV_CC_IPIR:
 361                 clearIPI(val);
 362                 break;
 363             case TSDEV_CC_ITIR:
 364                 clearITI(val);
 365                 break;
 366             case TSDEV_CC_IPIQ:
 367                 reqIPI(val);
 368                 break;
 369             default:
 370               panic("default in cchip read reached, accessing 0x%x\n");
 371         }  // swtich(regnum)
 372     } // not BIG_TSUNAMI write
 373     pkt.result = Success;
 374     return pioDelay;
 375 }
 376
 377 void
 378 TsunamiCChip::clearIPI(uint64_t ipintr)
 379 {
 380     int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
 381     assert(numcpus <= Tsunami::Max_CPUs);
 382
 383     if (ipintr) {
 384         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 385             // Check each cpu bit
 386             uint64_t cpumask = ULL(1) << cpunum;
 387             if (ipintr & cpumask) {
 388                 // Check if there is a pending ipi
 389                 if (ipint & cpumask) {
 390                     ipint &= ~cpumask;
 391                     tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 392                     DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
 393                 }
 394                 else
 395                     warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
 396             }
 397         }
 398     }
 399     else
 400         panic("Big IPI Clear, but not processors indicated\n");
 401 }
 402
 403 void
 404 TsunamiCChip::clearITI(uint64_t itintr)
 405 {
 406     int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
 407     assert(numcpus <= Tsunami::Max_CPUs);
 408
 409     if (itintr) {
 410         for (int i=0; i < numcpus; i++) {
 411             uint64_t cpumask = ULL(1) << i;
 412             if (itintr & cpumask & itint) {
 413                 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
 414                 itint &= ~cpumask;
 415                 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
 416             }
 417         }
 418     }
 419     else
 420         panic("Big ITI Clear, but not processors indicated\n");
 421 }
 422
 423 void
 424 TsunamiCChip::reqIPI(uint64_t ipreq)
 425 {
 426     int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
 427     assert(numcpus <= Tsunami::Max_CPUs);
 428
 429     if (ipreq) {
 430         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 431             // Check each cpu bit
 432             uint64_t cpumask = ULL(1) << cpunum;
 433             if (ipreq & cpumask) {
 434                 // Check if there is already an ipi (bits 8:11)
 435                 if (!(ipint & cpumask)) {
 436                     ipint  |= cpumask;
 437                     tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 438                     DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
 439                 }
 440                 else
 441                     warn("post IPI for CPU=%d, but IPI already\n", cpunum);
 442             }
 443         }
 444     }
 445     else
 446         panic("Big IPI Request, but not processors indicated\n");
 447 }
 448
 449
 450 void
 451 TsunamiCChip::postRTC()
 452 {
 453     int size = tsunami->intrctrl->cpu->system->execContexts.size();
 454     assert(size <= Tsunami::Max_CPUs);
 455
 456     for (int i = 0; i < size; i++) {
 457         uint64_t cpumask = ULL(1) << i;
 458        if (!(cpumask & itint)) {
 459            itint |= cpumask;
 460            tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
 461            DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
 462        }
 463     }
 464
 465 }
 466
 467 void
 468 TsunamiCChip::postDRIR(uint32_t interrupt)
 469 {
 470     uint64_t bitvector = ULL(1) << interrupt;
 471     uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
 472     assert(size <= Tsunami::Max_CPUs);
 473     drir |= bitvector;
 474
 475     for(int i=0; i < size; i++) {
 476         dir[i] = dim[i] & drir;
 477        if (dim[i] & bitvector) {
 478               tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
 479               DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
 480                         "interrupt %d\n",i, interrupt);
 481        }
 482     }
 483 }
 484
 485 void
 486 TsunamiCChip::clearDRIR(uint32_t interrupt)
 487 {
 488     uint64_t bitvector = ULL(1) << interrupt;
 489     uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
 490     assert(size <= Tsunami::Max_CPUs);
 491
 492     if (drir & bitvector)
 493     {
 494         drir &= ~bitvector;
 495         for(int i=0; i < size; i++) {
 496            if (dir[i] & bitvector) {
 497                tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
 498                DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
 499                     "interrupt %d\n",i, interrupt);
 500
 501            }
 502            dir[i] = dim[i] & drir;
 503         }
 504     }
 505     else
 506         DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
 507 }
 508
 509
 510 void
 511 TsunamiCChip::serialize(std::ostream &os)
 512 {
 513     SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 514     SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 515     SERIALIZE_SCALAR(ipint);
 516     SERIALIZE_SCALAR(itint);
 517     SERIALIZE_SCALAR(drir);
 518 }
 519
 520 void
 521 TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
 522 {
 523     UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
 524     UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
 525     UNSERIALIZE_SCALAR(ipint);
 526     UNSERIALIZE_SCALAR(itint);
 527     UNSERIALIZE_SCALAR(drir);
 528 }
 529
 530 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 531
 532     Param<Addr> pio_addr;
 533     Param<Tick> pio_latency;
 534     SimObjectParam<Platform *> platform;
 535     SimObjectParam<System *> system;
 536     SimObjectParam<Tsunami *> tsunami;
 537
 538 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 539
 540 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 541
 542     INIT_PARAM(pio_addr, "Device Address"),
 543     INIT_PARAM(pio_latency, "Programmed IO latency"),
 544     INIT_PARAM(platform, "platform"),
 545     INIT_PARAM(system, "system object"),
 546     INIT_PARAM(tsunami, "Tsunami")
 547
 548 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 549
 550 CREATE_SIM_OBJECT(TsunamiCChip)
 551 {
 552     TsunamiCChip::Params *p = new TsunamiCChip::Params;
 553     p->name = getInstanceName();
 554     p->pio_addr = pio_addr;
 555     p->pio_delay = pio_latency;
 556     p->platform = platform;
 557     p->system = system;
 558     p->tsunami = tsunami;
 559     return new TsunamiCChip(p);
 560 }
 561
 562 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)