dev/tsunami_cchip.cc

   1 /* $Id$ */
   2
   3 /* @file
   4  * Tsunami CChip (processor, memory, or IO)
   5  */
   6
   7 #include <deque>
   8 #include <string>
   9 #include <vector>
  10
  11 #include "base/trace.hh"
  12 #include "cpu/exec_context.hh"
  13 #include "dev/console.hh"
  14 #include "dev/etherdev.hh"
  15 #include "dev/scsi_ctrl.hh"
  16 #include "dev/tlaser_clock.hh"
  17 #include "dev/tsunami_cchip.hh"
  18 #include "dev/tsunamireg.h"
  19 #include "dev/tsunami.hh"
  20 #include "cpu/intr_control.hh"
  21 #include "mem/functional_mem/memory_control.hh"
  22 #include "sim/builder.hh"
  23 #include "sim/system.hh"
  24
  25 using namespace std;
  26
  27 TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
  28                        Addr addr, Addr mask, MemoryController *mmu)
  29     : MmapDevice(name, addr, mask, mmu), tsunami(t)
  30 {
  31     for(int i=0; i < Tsunami::Max_CPUs; i++) {
  32         dim[i] = 0;
  33         dir[i] = 0;
  34     }
  35
  36     drir = 0;
  37     misc = 0;
  38     RTCInterrupting = false;
  39
  40     //Put back pointer in tsunami
  41     tsunami->cchip = this;
  42 }
  43
  44 Fault
  45 TsunamiCChip::read(MemReqPtr req, uint8_t *data)
  46 {
  47     DPRINTF(Tsunami, "read  va=%#x size=%d\n",
  48             req->vaddr, req->size);
  49
  50     Addr daddr = (req->paddr & addr_mask) >> 6;
  51 //    ExecContext *xc = req->xc;
  52 //    int cpuid = xc->cpu_id;
  53
  54     switch (req->size) {
  55
  56       case sizeof(uint64_t):
  57           switch(daddr) {
  58               case TSDEV_CC_CSR:
  59                   *(uint64_t*)data = 0x0;
  60                   return No_Fault;
  61               case TSDEV_CC_MTR:
  62                   panic("TSDEV_CC_MTR not implemeted\n");
  63                    return No_Fault;
  64               case TSDEV_CC_MISC:
  65                 *(uint64_t*)data = misc;
  66                   return No_Fault;
  67               case TSDEV_CC_AAR0:
  68               case TSDEV_CC_AAR1:
  69               case TSDEV_CC_AAR2:
  70               case TSDEV_CC_AAR3:
  71                   panic("TSDEV_CC_AARx not implemeted\n");
  72                   return No_Fault;
  73               case TSDEV_CC_DIM0:
  74                   *(uint64_t*)data = dim[0];
  75                   return No_Fault;
  76               case TSDEV_CC_DIM1:
  77                   *(uint64_t*)data = dim[1];
  78                   return No_Fault;
  79               case TSDEV_CC_DIM2:
  80                   *(uint64_t*)data = dim[2];
  81                   return No_Fault;
  82               case TSDEV_CC_DIM3:
  83                   *(uint64_t*)data = dim[3];
  84                   return No_Fault;
  85               case TSDEV_CC_DIR0:
  86                   *(uint64_t*)data = dir[0];
  87                   return No_Fault;
  88               case TSDEV_CC_DIR1:
  89                   *(uint64_t*)data = dir[1];
  90                   return No_Fault;
  91               case TSDEV_CC_DIR2:
  92                   *(uint64_t*)data = dir[2];
  93                   return No_Fault;
  94               case TSDEV_CC_DIR3:
  95                   *(uint64_t*)data = dir[3];
  96                   return No_Fault;
  97               case TSDEV_CC_DRIR:
  98                   *(uint64_t*)data = drir;
  99                   return No_Fault;
 100               case TSDEV_CC_PRBEN:
 101                   panic("TSDEV_CC_PRBEN not implemented\n");
 102                   return No_Fault;
 103               case TSDEV_CC_IIC0:
 104               case TSDEV_CC_IIC1:
 105               case TSDEV_CC_IIC2:
 106               case TSDEV_CC_IIC3:
 107                   panic("TSDEV_CC_IICx not implemented\n");
 108                   return No_Fault;
 109               case TSDEV_CC_MPR0:
 110               case TSDEV_CC_MPR1:
 111               case TSDEV_CC_MPR2:
 112               case TSDEV_CC_MPR3:
 113                   panic("TSDEV_CC_MPRx not implemented\n");
 114                   return No_Fault;
 115               default:
 116                   panic("default in cchip read reached, accessing 0x%x\n");
 117            } // uint64_t
 118
 119       break;
 120       case sizeof(uint32_t):
 121       case sizeof(uint16_t):
 122       case sizeof(uint8_t):
 123       default:
 124         panic("invalid access size(?) for tsunami register!\n");
 125     }
 126     DPRINTFN("Tsunami CChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
 127
 128     return No_Fault;
 129 }
 130
 131 Fault
 132 TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
 133 {
 134     DPRINTF(Tsunami, "write - va=%#x size=%d \n",
 135             req->vaddr, req->size);
 136
 137     Addr daddr = (req->paddr & addr_mask) >> 6;
 138
 139     switch (req->size) {
 140
 141       case sizeof(uint64_t):
 142           switch(daddr) {
 143               case TSDEV_CC_CSR:
 144                   panic("TSDEV_CC_CSR write\n");
 145                   return No_Fault;
 146               case TSDEV_CC_MTR:
 147                   panic("TSDEV_CC_MTR write not implemented\n");
 148                    return No_Fault;
 149               case TSDEV_CC_MISC:
 150                 //If it is the seventh bit, clear the RTC interrupt
 151                 if ((*(uint64_t*) data) & (1<<4)) {
 152                     RTCInterrupting = false;
 153                     tsunami->intrctrl->clear(0, TheISA::INTLEVEL_IRQ2, 0);
 154                     DPRINTF(Tsunami, "clearing rtc interrupt\n");
 155                     misc &= ~(1<<4);
 156                 } else panic("TSDEV_CC_MISC write not implemented\n");
 157                   return No_Fault;
 158               case TSDEV_CC_AAR0:
 159               case TSDEV_CC_AAR1:
 160               case TSDEV_CC_AAR2:
 161               case TSDEV_CC_AAR3:
 162                   panic("TSDEV_CC_AARx write not implemeted\n");
 163                   return No_Fault;
 164               case TSDEV_CC_DIM0:
 165                    dim[0] = *(uint64_t*)data;
 166                   return No_Fault;
 167               case TSDEV_CC_DIM1:
 168                   dim[1] = *(uint64_t*)data;
 169                   return No_Fault;
 170               case TSDEV_CC_DIM2:
 171                   dim[2] = *(uint64_t*)data;
 172                   return No_Fault;
 173               case TSDEV_CC_DIM3:
 174                   dim[3] = *(uint64_t*)data;
 175                   return No_Fault;
 176               case TSDEV_CC_DIR0:
 177               case TSDEV_CC_DIR1:
 178               case TSDEV_CC_DIR2:
 179               case TSDEV_CC_DIR3:
 180                   panic("TSDEV_CC_DIR write not implemented\n");
 181                   return No_Fault;
 182               case TSDEV_CC_DRIR:
 183                   panic("TSDEV_CC_DRIR write not implemented\n");
 184                   return No_Fault;
 185               case TSDEV_CC_PRBEN:
 186                   panic("TSDEV_CC_PRBEN write not implemented\n");
 187                   return No_Fault;
 188               case TSDEV_CC_IIC0:
 189               case TSDEV_CC_IIC1:
 190               case TSDEV_CC_IIC2:
 191               case TSDEV_CC_IIC3:
 192                   panic("TSDEV_CC_IICx write not implemented\n");
 193                   return No_Fault;
 194               case TSDEV_CC_MPR0:
 195               case TSDEV_CC_MPR1:
 196               case TSDEV_CC_MPR2:
 197               case TSDEV_CC_MPR3:
 198                   panic("TSDEV_CC_MPRx write not implemented\n");
 199                   return No_Fault;
 200               default:
 201                   panic("default in cchip read reached, accessing 0x%x\n");
 202           }
 203
 204       break;
 205       case sizeof(uint32_t):
 206       case sizeof(uint16_t):
 207       case sizeof(uint8_t):
 208       default:
 209         panic("invalid access size(?) for tsunami register!\n");
 210     }
 211
 212     DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
 213
 214     return No_Fault;
 215 }
 216
 217 void
 218 TsunamiCChip::serialize(std::ostream &os)
 219 {
 220     // code should be written
 221 }
 222
 223 void
 224 TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
 225 {
 226     //code should be written
 227 }
 228
 229 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 230
 231     SimObjectParam<Tsunami *> tsunami;
 232     SimObjectParam<MemoryController *> mmu;
 233     Param<Addr> addr;
 234     Param<Addr> mask;
 235
 236 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
 237
 238 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 239
 240     INIT_PARAM(tsunami, "Tsunami"),
 241     INIT_PARAM(mmu, "Memory Controller"),
 242     INIT_PARAM(addr, "Device Address"),
 243     INIT_PARAM(mask, "Address Mask")
 244
 245 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
 246
 247 CREATE_SIM_OBJECT(TsunamiCChip)
 248 {
 249     return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu);
 250 }
 251
 252 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)