2 * Copyright (c) 2004 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * Emulation of the Tsunami CChip CSRs
37 #include "base/trace.hh"
38 #include "dev/tsunami_cchip.hh"
39 #include "dev/tsunamireg.h"
40 #include "dev/tsunami.hh"
41 #include "mem/bus/bus.hh"
42 #include "mem/bus/pio_interface.hh"
43 #include "mem/bus/pio_interface_impl.hh"
44 #include "mem/functional_mem/memory_control.hh"
45 #include "cpu/intr_control.hh"
46 #include "sim/builder.hh"
47 #include "sim/system.hh"
51 TsunamiCChip::TsunamiCChip(const string
&name
, Tsunami
*t
, Addr a
,
52 MemoryController
*mmu
, HierParams
*hier
, Bus
* bus
,
54 : PioDevice(name
, t
), addr(a
), tsunami(t
)
56 mmu
->add_child(this, RangeSize(addr
, size
));
59 pioInterface
= newPioInterface(name
, hier
, bus
, this,
60 &TsunamiCChip::cacheAccess
);
61 pioInterface
->addAddrRange(RangeSize(addr
, size
));
62 pioLatency
= pio_latency
* bus
->clockRatio
;
69 for (int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
75 //Put back pointer in tsunami
76 tsunami
->cchip
= this;
80 TsunamiCChip::read(MemReqPtr
&req
, uint8_t *data
)
82 DPRINTF(Tsunami
, "read va=%#x size=%d\n", req
->vaddr
, req
->size
);
84 Addr regnum
= (req
->paddr
- (addr
& EV5::PAddrImplMask
)) >> 6;
85 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
87 ExecContext
*xc
= req
->xc
;
91 case sizeof(uint64_t):
92 if (daddr
& TSDEV_CC_BDIMS
)
94 *(uint64_t*)data
= dim
[(daddr
>> 4) & 0x3F];
98 if (daddr
& TSDEV_CC_BDIRS
)
100 *(uint64_t*)data
= dir
[(daddr
>> 4) & 0x3F];
106 *(uint64_t*)data
= 0x0;
109 panic("TSDEV_CC_MTR not implemeted\n");
112 *(uint64_t*)data
= (ipint
<< 8) & 0xF |
120 *(uint64_t*)data
= 0;
123 *(uint64_t*)data
= dim
[0];
126 *(uint64_t*)data
= dim
[1];
129 *(uint64_t*)data
= dim
[2];
132 *(uint64_t*)data
= dim
[3];
135 *(uint64_t*)data
= dir
[0];
138 *(uint64_t*)data
= dir
[1];
141 *(uint64_t*)data
= dir
[2];
144 *(uint64_t*)data
= dir
[3];
147 *(uint64_t*)data
= drir
;
150 panic("TSDEV_CC_PRBEN not implemented\n");
156 panic("TSDEV_CC_IICx not implemented\n");
162 panic("TSDEV_CC_MPRx not implemented\n");
165 *(uint64_t*)data
= ipint
;
168 *(uint64_t*)data
= itint
;
171 panic("default in cchip read reached, accessing 0x%x\n");
175 case sizeof(uint32_t):
176 case sizeof(uint16_t):
177 case sizeof(uint8_t):
179 panic("invalid access size(?) for tsunami register!\n");
181 DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum
, req
->size
);
187 TsunamiCChip::write(MemReqPtr
&req
, const uint8_t *data
)
189 DPRINTF(Tsunami
, "write - va=%#x value=%#x size=%d \n",
190 req
->vaddr
, *(uint64_t*)data
, req
->size
);
192 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
193 Addr regnum
= (req
->paddr
- (addr
& EV5::PAddrImplMask
)) >> 6;
195 bool supportedWrite
= false;
199 case sizeof(uint64_t):
200 if (daddr
& TSDEV_CC_BDIMS
)
202 int number
= (daddr
>> 4) & 0x3F;
208 olddim
= dim
[number
];
209 olddir
= dir
[number
];
210 dim
[number
] = *(uint64_t*)data
;
211 dir
[number
] = dim
[number
] & drir
;
212 for(int x
= 0; x
< Tsunami::Max_CPUs
; x
++)
214 bitvector
= ULL(1) << x
;
215 // Figure out which bits have changed
216 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
218 // The bit is now set and it wasn't before (set)
219 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
221 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
222 DPRINTF(Tsunami
, "dim write resulting in posting dir"
223 " interrupt to cpu %d\n", number
);
225 else if ((olddir
& bitvector
) &&
226 !(dir
[number
] & bitvector
))
228 // The bit was set and now its now clear and
229 // we were interrupting on that bit before
230 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
231 DPRINTF(Tsunami
, "dim write resulting in clear"
232 " dir interrupt to cpu %d\n", number
);
244 panic("TSDEV_CC_CSR write\n");
247 panic("TSDEV_CC_MTR write not implemented\n");
251 ipreq
= (*(uint64_t*)data
>> 12) & 0xF;
252 //If it is bit 12-15, this is an IPI post
255 supportedWrite
= true;
258 //If it is bit 8-11, this is an IPI clear
260 ipintr
= (*(uint64_t*)data
>> 8) & 0xF;
263 supportedWrite
= true;
266 //If it is the 4-7th bit, clear the RTC interrupt
268 itintr
= (*(uint64_t*)data
>> 4) & 0xF;
271 supportedWrite
= true;
275 if (*(uint64_t*)data
& 0x10000000)
276 supportedWrite
= true;
279 panic("TSDEV_CC_MISC write not implemented\n");
286 panic("TSDEV_CC_AARx write not implemeted\n");
293 if(regnum
== TSDEV_CC_DIM0
)
295 else if(regnum
== TSDEV_CC_DIM1
)
297 else if(regnum
== TSDEV_CC_DIM2
)
306 olddim
= dim
[number
];
307 olddir
= dir
[number
];
308 dim
[number
] = *(uint64_t*)data
;
309 dir
[number
] = dim
[number
] & drir
;
310 for(int x
= 0; x
< 64; x
++)
312 bitvector
= ULL(1) << x
;
313 // Figure out which bits have changed
314 if ((dim
[number
] & bitvector
) != (olddim
& bitvector
))
316 // The bit is now set and it wasn't before (set)
317 if((dim
[number
] & bitvector
) && (dir
[number
] & bitvector
))
319 tsunami
->intrctrl
->post(number
, TheISA::INTLEVEL_IRQ1
, x
);
320 DPRINTF(Tsunami
, "posting dir interrupt to cpu 0\n");
322 else if ((olddir
& bitvector
) &&
323 !(dir
[number
] & bitvector
))
325 // The bit was set and now its now clear and
326 // we were interrupting on that bit before
327 tsunami
->intrctrl
->clear(number
, TheISA::INTLEVEL_IRQ1
, x
);
328 DPRINTF(Tsunami
, "dim write resulting in clear"
329 " dir interrupt to cpu %d\n",
342 panic("TSDEV_CC_DIR write not implemented\n");
344 panic("TSDEV_CC_DRIR write not implemented\n");
346 panic("TSDEV_CC_PRBEN write not implemented\n");
351 panic("TSDEV_CC_IICx write not implemented\n");
356 panic("TSDEV_CC_MPRx write not implemented\n");
358 clearIPI(*(uint64_t*)data
);
361 clearITI(*(uint64_t*)data
);
364 reqIPI(*(uint64_t*)data
);
367 panic("default in cchip read reached, accessing 0x%x\n");
371 case sizeof(uint32_t):
372 case sizeof(uint16_t):
373 case sizeof(uint8_t):
375 panic("invalid access size(?) for tsunami register!\n");
378 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr
, req
->size
);
384 TsunamiCChip::clearIPI(uint64_t ipintr
)
386 int numcpus
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
387 assert(numcpus
<= Tsunami::Max_CPUs
);
390 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
391 // Check each cpu bit
392 uint64_t cpumask
= ULL(1) << cpunum
;
393 if (ipintr
& cpumask
) {
394 // Check if there is a pending ipi
395 if (ipint
& cpumask
) {
397 tsunami
->intrctrl
->clear(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
398 DPRINTF(IPI
, "clear IPI IPI cpu=%d\n", cpunum
);
401 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum
);
406 panic("Big IPI Clear, but not processors indicated\n");
410 TsunamiCChip::clearITI(uint64_t itintr
)
412 int numcpus
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
413 assert(numcpus
<= Tsunami::Max_CPUs
);
416 for (int i
=0; i
< numcpus
; i
++) {
417 uint64_t cpumask
= ULL(1) << i
;
418 if (itintr
& cpumask
& itint
) {
419 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ2
, 0);
421 DPRINTF(Tsunami
, "clearing rtc interrupt to cpu=%d\n", i
);
426 panic("Big ITI Clear, but not processors indicated\n");
430 TsunamiCChip::reqIPI(uint64_t ipreq
)
432 int numcpus
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
433 assert(numcpus
<= Tsunami::Max_CPUs
);
436 for (int cpunum
=0; cpunum
< numcpus
; cpunum
++) {
437 // Check each cpu bit
438 uint64_t cpumask
= ULL(1) << cpunum
;
439 if (ipreq
& cpumask
) {
440 // Check if there is already an ipi (bits 8:11)
441 if (!(ipint
& cpumask
)) {
443 tsunami
->intrctrl
->post(cpunum
, TheISA::INTLEVEL_IRQ3
, 0);
444 DPRINTF(IPI
, "send IPI cpu=%d\n", cpunum
);
447 warn("post IPI for CPU=%d, but IPI already\n", cpunum
);
452 panic("Big IPI Request, but not processors indicated\n");
457 TsunamiCChip::postRTC()
459 int size
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
460 assert(size
<= Tsunami::Max_CPUs
);
462 for (int i
= 0; i
< size
; i
++) {
463 uint64_t cpumask
= ULL(1) << i
;
464 if (!(cpumask
& itint
)) {
466 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ2
, 0);
467 DPRINTF(Tsunami
, "Posting RTC interrupt to cpu=%d", i
);
474 TsunamiCChip::postDRIR(uint32_t interrupt
)
476 uint64_t bitvector
= ULL(1) << interrupt
;
477 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
478 assert(size
<= Tsunami::Max_CPUs
);
481 for(int i
=0; i
< size
; i
++) {
482 dir
[i
] = dim
[i
] & drir
;
483 if (dim
[i
] & bitvector
) {
484 tsunami
->intrctrl
->post(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
485 DPRINTF(Tsunami
, "posting dir interrupt to cpu %d,"
486 "interrupt %d\n",i
, interrupt
);
492 TsunamiCChip::clearDRIR(uint32_t interrupt
)
494 uint64_t bitvector
= ULL(1) << interrupt
;
495 uint64_t size
= tsunami
->intrctrl
->cpu
->system
->execContexts
.size();
496 assert(size
<= Tsunami::Max_CPUs
);
498 if (drir
& bitvector
)
501 for(int i
=0; i
< size
; i
++) {
502 if (dir
[i
] & bitvector
) {
503 tsunami
->intrctrl
->clear(i
, TheISA::INTLEVEL_IRQ1
, interrupt
);
504 DPRINTF(Tsunami
, "clearing dir interrupt to cpu %d,"
505 "interrupt %d\n",i
, interrupt
);
508 dir
[i
] = dim
[i
] & drir
;
512 DPRINTF(Tsunami
, "Spurrious clear? interrupt %d\n", interrupt
);
516 TsunamiCChip::cacheAccess(MemReqPtr
&req
)
518 return curTick
+ pioLatency
;
523 TsunamiCChip::serialize(std::ostream
&os
)
525 SERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
526 SERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
527 SERIALIZE_SCALAR(ipint
);
528 SERIALIZE_SCALAR(itint
);
529 SERIALIZE_SCALAR(drir
);
533 TsunamiCChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
535 UNSERIALIZE_ARRAY(dim
, Tsunami::Max_CPUs
);
536 UNSERIALIZE_ARRAY(dir
, Tsunami::Max_CPUs
);
537 UNSERIALIZE_SCALAR(ipint
);
538 UNSERIALIZE_SCALAR(itint
);
539 UNSERIALIZE_SCALAR(drir
);
542 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
544 SimObjectParam
<Tsunami
*> tsunami
;
545 SimObjectParam
<MemoryController
*> mmu
;
547 SimObjectParam
<Bus
*> io_bus
;
548 Param
<Tick
> pio_latency
;
549 SimObjectParam
<HierParams
*> hier
;
551 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip
)
553 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
555 INIT_PARAM(tsunami
, "Tsunami"),
556 INIT_PARAM(mmu
, "Memory Controller"),
557 INIT_PARAM(addr
, "Device Address"),
558 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
559 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
560 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
562 END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip
)
564 CREATE_SIM_OBJECT(TsunamiCChip
)
566 return new TsunamiCChip(getInstanceName(), tsunami
, addr
, mmu
, hier
,
567 io_bus
, pio_latency
);
570 REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip
)