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30 * Emulation of the Tsunami CChip CSRs
33 #ifndef __TSUNAMI_CCHIP_HH__
34 #define __TSUNAMI_CCHIP_HH__
36 #include "dev/tsunami.hh"
37 #include "base/range.hh"
38 #include "dev/io_device.hh"
43 class TsunamiCChip : public PioDevice
46 /** The base address of this device */
49 /** The size of mappad from the above address */
50 static const Addr size = 0xfffffff;
54 * pointer to the tsunami object.
55 * This is our access to all the other tsunami
61 * The dims are device interrupt mask registers.
62 * One exists for each CPU, the DRIR X DIM = DIR
64 uint64_t dim[Tsunami::Max_CPUs];
67 * The dirs are device interrupt registers.
68 * One exists for each CPU, the DRIR X DIM = DIR
70 uint64_t dir[Tsunami::Max_CPUs];
73 * This register contains bits for each PCI interrupt
78 /** Indicator of which CPUs have an IPI interrupt */
81 /** Indicator of which CPUs have an RTC interrupt */
86 * Initialize the Tsunami CChip by setting all of the
87 * device register to 0.
88 * @param name name of this device.
89 * @param t pointer back to the Tsunami object that we belong to.
90 * @param a address we are mapped at.
91 * @param mmu pointer to the memory controller that sends us events.
92 * @param hier object to store parameters universal the device hierarchy
93 * @param bus The bus that this device is attached to
95 TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
96 MemoryController *mmu, HierParams *hier, Bus *bus,
100 * Process a read to the CChip.
101 * @param req Contains the address to read from.
102 * @param data A pointer to write the read data to.
103 * @return The fault condition of the access.
105 virtual Fault read(MemReqPtr &req, uint8_t *data);
109 * Process a write to the CChip.
110 * @param req Contains the address to write to.
111 * @param data The data to write.
112 * @return The fault condition of the access.
114 virtual Fault write(MemReqPtr &req, const uint8_t *data);
117 * post an RTC interrupt to the CPU
122 * post an interrupt to the CPU.
123 * @param interrupt the interrupt number to post (0-64)
125 void postDRIR(uint32_t interrupt);
128 * clear an interrupt previously posted to the CPU.
129 * @param interrupt the interrupt number to post (0-64)
131 void clearDRIR(uint32_t interrupt);
134 * post an ipi interrupt to the CPU.
135 * @param ipintr the cpu number to clear(bitvector)
137 void clearIPI(uint64_t ipintr);
140 * clear a timer interrupt previously posted to the CPU.
141 * @param interrupt the cpu number to clear(bitvector)
143 void clearITI(uint64_t itintr);
146 * request an interrupt be posted to the CPU.
147 * @param ipreq the cpu number to interrupt(bitvector)
149 void reqIPI(uint64_t ipreq);
153 * Serialize this object to the given output stream.
154 * @param os The stream to serialize to.
156 virtual void serialize(std::ostream &os);
159 * Reconstruct the state of this object from a checkpoint.
160 * @param cp The checkpoint use.
161 * @param section The section name of this object
163 virtual void unserialize(Checkpoint *cp, const std::string §ion);
166 * Return how long this access will take.
167 * @param req the memory request to calcuate
168 * @return Tick when the request is done
170 Tick cacheAccess(MemReqPtr &req);
173 #endif // __TSUNAMI_CCHIP_HH__