2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Emulation of the Tsunami CChip CSRs
33 #ifndef __TSUNAMI_CCHIP_HH__
34 #define __TSUNAMI_CCHIP_HH__
36 #include "mem/functional_mem/functional_memory.hh"
37 #include "dev/tsunami.hh"
42 class TsunamiCChip : public FunctionalMemory
46 static const Addr size = 0xfff;
50 * pointer to the tsunami object.
51 * This is our access to all the other tsunami
57 * The dims are device interrupt mask registers.
58 * One exists for each CPU, the DRIR X DIM = DIR
60 uint64_t dim[Tsunami::Max_CPUs];
63 * The dirs are device interrupt registers.
64 * One exists for each CPU, the DRIR X DIM = DIR
66 uint64_t dir[Tsunami::Max_CPUs];
67 bool dirInterrupting[Tsunami::Max_CPUs];
70 * This register contains bits for each PCI interrupt
76 TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
77 MemoryController *mmu);
79 virtual Fault read(MemReqPtr &req, uint8_t *data);
80 virtual Fault write(MemReqPtr &req, const uint8_t *data);
82 void postDRIR(uint64_t bitvector);
83 void clearDRIR(uint64_t bitvector);
85 virtual void serialize(std::ostream &os);
86 virtual void unserialize(Checkpoint *cp, const std::string §ion);
92 #endif // __TSUNAMI_CCHIP_HH__