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30 * Emulation of the Tsunami CChip CSRs
33 #ifndef __TSUNAMI_CCHIP_HH__
34 #define __TSUNAMI_CCHIP_HH__
36 #include "dev/tsunami.hh"
37 #include "base/range.hh"
38 #include "dev/io_device.hh"
43 class TsunamiCChip : public PioDevice
46 /** The base address of this device */
49 /** The size of mappad from the above address */
50 static const Addr size = 0xfff;
54 * pointer to the tsunami object.
55 * This is our access to all the other tsunami
61 * The dims are device interrupt mask registers.
62 * One exists for each CPU, the DRIR X DIM = DIR
64 uint64_t dim[Tsunami::Max_CPUs];
67 * The dirs are device interrupt registers.
68 * One exists for each CPU, the DRIR X DIM = DIR
70 uint64_t dir[Tsunami::Max_CPUs];
71 bool dirInterrupting[Tsunami::Max_CPUs];
74 * This register contains bits for each PCI interrupt
80 * The MISC register contains the CPU we are currently on
81 * as well as bits to ack RTC and IPI interrupts.
85 /** Count of the number of pending IPIs on a CPU */
86 uint64_t ipiInterrupting[Tsunami::Max_CPUs];
88 /** Indicator of which CPUs have had an RTC interrupt */
89 bool RTCInterrupting[Tsunami::Max_CPUs];
93 * Initialize the Tsunami CChip by setting all of the
94 * device register to 0.
95 * @param name name of this device.
96 * @param t pointer back to the Tsunami object that we belong to.
97 * @param a address we are mapped at.
98 * @param mmu pointer to the memory controller that sends us events.
99 * @param hier object to store parameters universal the device hierarchy
100 * @param bus The bus that this device is attached to
102 TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
103 MemoryController *mmu, HierParams *hier, Bus *bus);
106 * Process a read to the CChip.
107 * @param req Contains the address to read from.
108 * @param data A pointer to write the read data to.
109 * @return The fault condition of the access.
111 virtual Fault read(MemReqPtr &req, uint8_t *data);
115 * Process a write to the CChip.
116 * @param req Contains the address to write to.
117 * @param data The data to write.
118 * @return The fault condition of the access.
120 virtual Fault write(MemReqPtr &req, const uint8_t *data);
123 * post an RTC interrupt to the CPU
128 * post an interrupt to the CPU.
129 * @param interrupt the interrupt number to post (0-64)
131 void postDRIR(uint32_t interrupt);
134 * clear an interrupt previously posted to the CPU.
135 * @param interrupt the interrupt number to post (0-64)
137 void clearDRIR(uint32_t interrupt);
140 * Serialize this object to the given output stream.
141 * @param os The stream to serialize to.
143 virtual void serialize(std::ostream &os);
146 * Reconstruct the state of this object from a checkpoint.
147 * @param cp The checkpoint use.
148 * @param section The section name of this object
150 virtual void unserialize(Checkpoint *cp, const std::string §ion);
153 * Return how long this access will take.
154 * @param req the memory request to calcuate
155 * @return Tick when the request is done
157 Tick cacheAccess(MemReqPtr &req);
160 #endif // __TSUNAMI_CCHIP_HH__