2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Tsunami I/O including PIC, PIT, RTC, DMA
39 #include "base/trace.hh"
40 #include "dev/tsunami_io.hh"
41 #include "dev/tsunami.hh"
42 #include "mem/bus/bus.hh"
43 #include "mem/bus/pio_interface.hh"
44 #include "mem/bus/pio_interface_impl.hh"
45 #include "sim/builder.hh"
46 #include "dev/tsunami_cchip.hh"
47 #include "dev/tsunamireg.h"
48 #include "dev/rtcreg.h"
49 #include "mem/functional_mem/memory_control.hh"
53 #define UNIX_YEAR_OFFSET 52
55 // Timer Event for Periodic interrupt of RTC
56 TsunamiIO::RTCEvent::RTCEvent(Tsunami
* t
)
57 : Event(&mainEventQueue
), tsunami(t
)
59 DPRINTF(MC146818
, "RTC Event Initilizing\n");
60 schedule(curTick
+ ticksPerSecond
/RTC_RATE
);
64 TsunamiIO::RTCEvent::process()
66 DPRINTF(MC146818
, "RTC Timer Interrupt\n");
67 schedule(curTick
+ ticksPerSecond
/RTC_RATE
);
68 //Actually interrupt the processor here
69 tsunami
->cchip
->postRTC();
73 TsunamiIO::RTCEvent::description()
75 return "tsunami RTC 1024Hz interrupt";
79 TsunamiIO::RTCEvent::serialize(std::ostream
&os
)
82 SERIALIZE_SCALAR(time
);
86 TsunamiIO::RTCEvent::unserialize(Checkpoint
*cp
, const std::string
§ion
)
89 UNSERIALIZE_SCALAR(time
);
94 // Timer Event for PIT Timers
95 TsunamiIO::ClockEvent::ClockEvent()
96 : Event(&mainEventQueue
)
98 /* This is the PIT Tick Rate. A constant for the 8254 timer. The
99 * Tsunami platform has one of these cycle counters on the Cypress
100 * South Bridge and it is used by linux for estimating the cycle
101 * frequency of the machine it is running on. --Ali
103 interval
= (Tick
)(Clock::Float::s
/ 1193180.0);
105 DPRINTF(Tsunami
, "Clock Event Initilizing\n");
110 TsunamiIO::ClockEvent::process()
112 DPRINTF(Tsunami
, "Timer Interrupt\n");
114 status
= 0x20; // set bit that linux is looking for
116 schedule(curTick
+ interval
);
120 TsunamiIO::ClockEvent::Program(int count
)
122 DPRINTF(Tsunami
, "Timer set to curTick + %d\n", count
);
123 schedule(curTick
+ count
* interval
);
128 TsunamiIO::ClockEvent::description()
130 return "tsunami 8254 Interval timer";
134 TsunamiIO::ClockEvent::ChangeMode(uint8_t md
)
140 TsunamiIO::ClockEvent::Status()
146 TsunamiIO::ClockEvent::serialize(std::ostream
&os
)
148 Tick time
= scheduled() ? when() : 0;
149 SERIALIZE_SCALAR(time
);
150 SERIALIZE_SCALAR(status
);
151 SERIALIZE_SCALAR(mode
);
152 SERIALIZE_SCALAR(interval
);
156 TsunamiIO::ClockEvent::unserialize(Checkpoint
*cp
, const std::string
§ion
)
159 UNSERIALIZE_SCALAR(time
);
160 UNSERIALIZE_SCALAR(status
);
161 UNSERIALIZE_SCALAR(mode
);
162 UNSERIALIZE_SCALAR(interval
);
167 TsunamiIO::TsunamiIO(const string
&name
, Tsunami
*t
, time_t init_time
,
168 Addr a
, MemoryController
*mmu
, HierParams
*hier
, Bus
*bus
,
170 : PioDevice(name
, t
), addr(a
), tsunami(t
), rtc(t
)
172 mmu
->add_child(this, RangeSize(addr
, size
));
175 pioInterface
= newPioInterface(name
, hier
, bus
, this,
176 &TsunamiIO::cacheAccess
);
177 pioInterface
->addAddrRange(RangeSize(addr
, size
));
178 pioLatency
= pio_latency
* bus
->clockRatio
;
181 // set the back pointer from tsunami to myself
185 set_time(init_time
== 0 ? time(NULL
) : init_time
);
188 picInterrupting
= false;
192 TsunamiIO::set_time(time_t t
)
195 DPRINTFN("Real-time clock set to %s", asctime(&tm
));
199 TsunamiIO::read(MemReqPtr
&req
, uint8_t *data
)
201 DPRINTF(Tsunami
, "io read va=%#x size=%d IOPorrt=%#x\n",
202 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff);
204 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
208 case sizeof(uint8_t):
211 // !!! If this is modified 64bit case needs to be too
212 // Pal code has to do a 64 bit physical read because there is
213 // no load physical byte instruction
214 *(uint8_t*)data
= picr
;
217 // PIC2 not implemnted... just return 0
218 *(uint8_t*)data
= 0x00;
221 *(uint8_t*)data
= timer2
.Status();
226 *(uint8_t*)data
= uip
<< 7 | 0x26;
230 // DM and 24/12 and UIE
231 *(uint8_t*)data
= 0x46;
234 // If we want to support RTC user access in linux
235 // This won't work, but for now it's fine
236 *(uint8_t*)data
= 0x00;
239 panic("RTC Control Register D not implemented");
241 *(uint8_t *)data
= tm
.tm_sec
;
244 *(uint8_t *)data
= tm
.tm_min
;
247 *(uint8_t *)data
= tm
.tm_hour
;
250 *(uint8_t *)data
= tm
.tm_wday
;
253 *(uint8_t *)data
= tm
.tm_mday
;
255 *(uint8_t *)data
= tm
.tm_mon
+ 1;
258 *(uint8_t *)data
= tm
.tm_year
- UNIX_YEAR_OFFSET
;
261 panic("Unknown RTC Address\n");
265 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
267 case sizeof(uint16_t):
268 case sizeof(uint32_t):
269 panic("I/O Read - invalid size - va %#x size %d\n",
270 req
->vaddr
, req
->size
);
272 case sizeof(uint64_t):
275 // !!! If this is modified 8bit case needs to be too
276 // Pal code has to do a 64 bit physical read because there is
277 // no load physical byte instruction
278 *(uint64_t*)data
= (uint64_t)picr
;
281 panic("I/O Read - invalid size - va %#x size %d\n",
282 req
->vaddr
, req
->size
);
286 panic("I/O Read - invalid size - va %#x size %d\n",
287 req
->vaddr
, req
->size
);
289 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
295 TsunamiIO::write(MemReqPtr
&req
, const uint8_t *data
)
299 uint8_t dt
= *(uint8_t*)data
;
303 DPRINTF(Tsunami
, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
304 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff, dt64
);
306 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
309 case sizeof(uint8_t):
311 case TSDEV_PIC1_MASK
:
312 mask1
= ~(*(uint8_t*)data
);
313 if ((picr
& mask1
) && !picInterrupting
) {
314 picInterrupting
= true;
315 tsunami
->cchip
->postDRIR(55);
316 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
318 if ((!(picr
& mask1
)) && picInterrupting
) {
319 picInterrupting
= false;
320 tsunami
->cchip
->clearDRIR(55);
321 DPRINTF(Tsunami
, "clearing pic interrupt\n");
324 case TSDEV_PIC2_MASK
:
325 mask2
= *(uint8_t*)data
;
326 //PIC2 Not implemented to interrupt
329 // clear the interrupt on the PIC
330 picr
&= ~(1 << (*(uint8_t*)data
& 0xF));
332 tsunami
->cchip
->clearDRIR(55);
336 case TSDEV_DMA1_RESET
:
338 case TSDEV_DMA2_RESET
:
340 case TSDEV_DMA1_MODE
:
341 mode1
= *(uint8_t*)data
;
343 case TSDEV_DMA2_MODE
:
344 mode2
= *(uint8_t*)data
;
346 case TSDEV_DMA1_MASK
:
347 case TSDEV_DMA2_MASK
:
352 if ((*(uint8_t*)data
& 0x30) != 0x30)
353 panic("Only L/M write supported\n");
355 switch(*(uint8_t*)data
>> 6) {
357 timer0
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
360 timer2
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
363 panic("Read Back Command not implemented\n");
366 case TSDEV_TMR2_DATA
:
367 /* two writes before we actually start the Timer
368 so I set a flag in the timerData */
369 if(timerData
& 0x1000) {
371 timerData
+= *(uint8_t*)data
<< 8;
372 timer2
.Program(timerData
);
374 timerData
= *(uint8_t*)data
;
378 case TSDEV_TMR0_DATA
:
379 /* two writes before we actually start the Timer
380 so I set a flag in the timerData */
381 if(timerData
& 0x1000) {
383 timerData
+= *(uint8_t*)data
<< 8;
384 timer0
.Program(timerData
);
386 timerData
= *(uint8_t*)data
;
391 RTCAddress
= *(uint8_t*)data
;
394 panic("RTC Write not implmented (rtc.o won't work)\n");
396 panic("I/O Write - va%#x size %d\n", req
->vaddr
, req
->size
);
398 case sizeof(uint16_t):
399 case sizeof(uint32_t):
400 case sizeof(uint64_t):
402 panic("I/O Write - invalid size - va %#x size %d\n",
403 req
->vaddr
, req
->size
);
411 TsunamiIO::postPIC(uint8_t bitvector
)
413 //PIC2 Is not implemented, because nothing of interest there
416 tsunami
->cchip
->postDRIR(55);
417 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
422 TsunamiIO::clearPIC(uint8_t bitvector
)
424 //PIC2 Is not implemented, because nothing of interest there
426 if (!(picr
& mask1
)) {
427 tsunami
->cchip
->clearDRIR(55);
428 DPRINTF(Tsunami
, "clearing pic interrupt to cchip\n");
433 TsunamiIO::cacheAccess(MemReqPtr
&req
)
435 return curTick
+ pioLatency
;
439 TsunamiIO::serialize(std::ostream
&os
)
441 SERIALIZE_SCALAR(timerData
);
442 SERIALIZE_SCALAR(uip
);
443 SERIALIZE_SCALAR(mask1
);
444 SERIALIZE_SCALAR(mask2
);
445 SERIALIZE_SCALAR(mode1
);
446 SERIALIZE_SCALAR(mode2
);
447 SERIALIZE_SCALAR(picr
);
448 SERIALIZE_SCALAR(picInterrupting
);
449 SERIALIZE_SCALAR(RTCAddress
);
451 // Serialize the timers
452 nameOut(os
, csprintf("%s.timer0", name()));
453 timer0
.serialize(os
);
454 nameOut(os
, csprintf("%s.timer2", name()));
455 timer2
.serialize(os
);
456 nameOut(os
, csprintf("%s.rtc", name()));
461 TsunamiIO::unserialize(Checkpoint
*cp
, const std::string
§ion
)
463 UNSERIALIZE_SCALAR(timerData
);
464 UNSERIALIZE_SCALAR(uip
);
465 UNSERIALIZE_SCALAR(mask1
);
466 UNSERIALIZE_SCALAR(mask2
);
467 UNSERIALIZE_SCALAR(mode1
);
468 UNSERIALIZE_SCALAR(mode2
);
469 UNSERIALIZE_SCALAR(picr
);
470 UNSERIALIZE_SCALAR(picInterrupting
);
471 UNSERIALIZE_SCALAR(RTCAddress
);
473 // Unserialize the timers
474 timer0
.unserialize(cp
, csprintf("%s.timer0", section
));
475 timer2
.unserialize(cp
, csprintf("%s.timer2", section
));
476 rtc
.unserialize(cp
, csprintf("%s.rtc", section
));
479 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
481 SimObjectParam
<Tsunami
*> tsunami
;
483 SimObjectParam
<MemoryController
*> mmu
;
485 SimObjectParam
<Bus
*> io_bus
;
486 Param
<Tick
> pio_latency
;
487 SimObjectParam
<HierParams
*> hier
;
489 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
491 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
493 INIT_PARAM(tsunami
, "Tsunami"),
494 INIT_PARAM_DFLT(time
, "System time to use "
495 "(0 for actual time, default is 1/1/06", ULL(1136073600)),
496 INIT_PARAM(mmu
, "Memory Controller"),
497 INIT_PARAM(addr
, "Device Address"),
498 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
499 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
500 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
502 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
504 CREATE_SIM_OBJECT(TsunamiIO
)
506 return new TsunamiIO(getInstanceName(), tsunami
, time
, addr
, mmu
, hier
,
507 io_bus
, pio_latency
);
510 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO
)