2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Tsunami I/O including PIC, PIT, RTC, DMA
39 #include "base/trace.hh"
40 #include "cpu/exec_context.hh"
41 #include "dev/console.hh"
42 #include "dev/tlaser_clock.hh"
43 #include "dev/tsunami_io.hh"
44 #include "dev/tsunamireg.h"
45 #include "dev/tsunami.hh"
46 #include "mem/functional_mem/memory_control.hh"
47 #include "sim/builder.hh"
48 #include "dev/tsunami_cchip.hh"
52 #define UNIX_YEAR_OFFSET 52
54 // Timer Event for Periodic interrupt of RTC
55 TsunamiIO::RTCEvent::RTCEvent(Tsunami
* t
)
56 : Event(&mainEventQueue
), tsunami(t
)
58 DPRINTF(MC146818
, "RTC Event Initilizing\n");
59 schedule(curTick
+ ticksPerSecond
/RTC_RATE
);
63 TsunamiIO::RTCEvent::process()
65 DPRINTF(MC146818
, "RTC Timer Interrupt\n");
66 schedule(curTick
+ ticksPerSecond
/RTC_RATE
);
67 //Actually interrupt the processor here
68 tsunami
->cchip
->postRTC();
73 TsunamiIO::RTCEvent::description()
75 return "tsunami RTC 1024Hz interrupt";
78 // Timer Event for PIT Timers
79 TsunamiIO::ClockEvent::ClockEvent()
80 : Event(&mainEventQueue
)
82 DPRINTF(Tsunami
, "Clock Event Initilizing\n");
87 TsunamiIO::ClockEvent::process()
89 DPRINTF(Tsunami
, "Timer Interrupt\n");
91 status
= 0x20; // set bit that linux is looking for
93 schedule(curTick
+ interval
);
97 TsunamiIO::ClockEvent::Program(int count
)
99 DPRINTF(Tsunami
, "Timer set to curTick + %d\n", count
);
100 // should be count * (cpufreq/pitfreq)
101 interval
= count
* ticksPerSecond
/1193180UL;
102 schedule(curTick
+ interval
);
107 TsunamiIO::ClockEvent::description()
109 return "tsunami 8254 Interval timer";
113 TsunamiIO::ClockEvent::ChangeMode(uint8_t md
)
119 TsunamiIO::ClockEvent::Status()
124 TsunamiIO::TsunamiIO(const string
&name
, Tsunami
*t
, time_t init_time
,
125 Addr a
, MemoryController
*mmu
)
126 : FunctionalMemory(name
), addr(a
), tsunami(t
), rtc(t
)
128 mmu
->add_child(this, Range
<Addr
>(addr
, addr
+ size
));
130 // set the back pointer from tsunami to myself
134 set_time(init_time
== 0 ? time(NULL
) : init_time
);
137 picInterrupting
= false;
141 TsunamiIO::set_time(time_t t
)
144 DPRINTFN("Real-time clock set to %s", asctime(&tm
));
148 TsunamiIO::read(MemReqPtr
&req
, uint8_t *data
)
150 DPRINTF(Tsunami
, "io read va=%#x size=%d IOPorrt=%#x\n",
151 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff);
153 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
));
157 case sizeof(uint8_t):
160 // !!! If this is modified 64bit case needs to be too
161 // Pal code has to do a 64 bit physical read because there is
162 // no load physical byte instruction
163 *(uint8_t*)data
= picr
;
166 // PIC2 not implemnted... just return 0
167 *(uint8_t*)data
= 0x00;
170 *(uint8_t*)data
= timer2
.Status();
174 case RTC_CONTROL_REGISTERA
:
175 *(uint8_t*)data
= uip
<< 7 | 0x26;
178 case RTC_CONTROL_REGISTERB
:
179 // DM and 24/12 and UIE
180 *(uint8_t*)data
= 0x46;
182 case RTC_CONTROL_REGISTERC
:
183 // If we want to support RTC user access in linux
184 // This won't work, but for now it's fine
185 *(uint8_t*)data
= 0x00;
187 case RTC_CONTROL_REGISTERD
:
188 panic("RTC Control Register D not implemented");
190 *(uint8_t *)data
= tm
.tm_sec
;
193 *(uint8_t *)data
= tm
.tm_min
;
196 *(uint8_t *)data
= tm
.tm_hour
;
198 case RTC_DAY_OF_WEEK
:
199 *(uint8_t *)data
= tm
.tm_wday
;
201 case RTC_DAY_OF_MONTH
:
202 *(uint8_t *)data
= tm
.tm_mday
;
204 *(uint8_t *)data
= tm
.tm_mon
+ 1;
207 *(uint8_t *)data
= tm
.tm_year
- UNIX_YEAR_OFFSET
;
210 panic("Unknown RTC Address\n");
214 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
216 case sizeof(uint16_t):
217 case sizeof(uint32_t):
218 panic("I/O Read - invalid size - va %#x size %d\n",
219 req
->vaddr
, req
->size
);
221 case sizeof(uint64_t):
224 // !!! If this is modified 8bit case needs to be too
225 // Pal code has to do a 64 bit physical read because there is
226 // no load physical byte instruction
227 *(uint64_t*)data
= (uint64_t)picr
;
230 panic("I/O Read - invalid size - va %#x size %d\n",
231 req
->vaddr
, req
->size
);
235 panic("I/O Read - invalid size - va %#x size %d\n",
236 req
->vaddr
, req
->size
);
238 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
244 TsunamiIO::write(MemReqPtr
&req
, const uint8_t *data
)
246 uint8_t dt
= *(uint8_t*)data
;
249 DPRINTF(Tsunami
, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
250 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff, dt64
);
252 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
));
255 case sizeof(uint8_t):
257 case TSDEV_PIC1_MASK
:
258 mask1
= ~(*(uint8_t*)data
);
259 if ((picr
& mask1
) && !picInterrupting
) {
260 picInterrupting
= true;
261 tsunami
->cchip
->postDRIR(55);
262 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
264 if ((!(picr
& mask1
)) && picInterrupting
) {
265 picInterrupting
= false;
266 tsunami
->cchip
->clearDRIR(55);
267 DPRINTF(Tsunami
, "clearing pic interrupt\n");
270 case TSDEV_PIC2_MASK
:
271 mask2
= *(uint8_t*)data
;
272 //PIC2 Not implemented to interrupt
275 // clear the interrupt on the PIC
276 picr
&= ~(1 << (*(uint8_t*)data
& 0xF));
278 tsunami
->cchip
->clearDRIR(55);
282 case TSDEV_DMA1_RESET
:
284 case TSDEV_DMA2_RESET
:
286 case TSDEV_DMA1_MODE
:
287 mode1
= *(uint8_t*)data
;
289 case TSDEV_DMA2_MODE
:
290 mode2
= *(uint8_t*)data
;
292 case TSDEV_DMA1_MASK
:
293 case TSDEV_DMA2_MASK
:
298 if ((*(uint8_t*)data
& 0x30) != 0x30)
299 panic("Only L/M write supported\n");
301 switch(*(uint8_t*)data
>> 6) {
303 timer0
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
306 timer2
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
309 panic("Read Back Command not implemented\n");
312 case TSDEV_TMR2_DATA
:
313 /* two writes before we actually start the Timer
314 so I set a flag in the timerData */
315 if(timerData
& 0x1000) {
317 timerData
+= *(uint8_t*)data
<< 8;
318 timer2
.Program(timerData
);
320 timerData
= *(uint8_t*)data
;
324 case TSDEV_TMR0_DATA
:
325 /* two writes before we actually start the Timer
326 so I set a flag in the timerData */
327 if(timerData
& 0x1000) {
329 timerData
+= *(uint8_t*)data
<< 8;
330 timer0
.Program(timerData
);
332 timerData
= *(uint8_t*)data
;
337 RTCAddress
= *(uint8_t*)data
;
340 panic("RTC Write not implmented (rtc.o won't work)\n");
342 panic("I/O Write - va%#x size %d\n", req
->vaddr
, req
->size
);
344 case sizeof(uint16_t):
345 case sizeof(uint32_t):
346 case sizeof(uint64_t):
348 panic("I/O Write - invalid size - va %#x size %d\n",
349 req
->vaddr
, req
->size
);
357 TsunamiIO::postPIC(uint8_t bitvector
)
359 //PIC2 Is not implemented, because nothing of interest there
362 tsunami
->cchip
->postDRIR(55);
363 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
368 TsunamiIO::clearPIC(uint8_t bitvector
)
370 //PIC2 Is not implemented, because nothing of interest there
372 if (!(picr
& mask1
)) {
373 tsunami
->cchip
->clearDRIR(55);
374 DPRINTF(Tsunami
, "clearing pic interrupt to cchip\n");
379 TsunamiIO::serialize(std::ostream
&os
)
381 SERIALIZE_SCALAR(timerData
);
382 SERIALIZE_SCALAR(uip
);
383 SERIALIZE_SCALAR(picr
);
384 SERIALIZE_SCALAR(picInterrupting
);
385 Tick time0when
= timer0
.when();
386 Tick time2when
= timer2
.when();
387 Tick rtcwhen
= rtc
.when();
388 SERIALIZE_SCALAR(time0when
);
389 SERIALIZE_SCALAR(time2when
);
390 SERIALIZE_SCALAR(rtcwhen
);
395 TsunamiIO::unserialize(Checkpoint
*cp
, const std::string
§ion
)
397 UNSERIALIZE_SCALAR(timerData
);
398 UNSERIALIZE_SCALAR(uip
);
399 UNSERIALIZE_SCALAR(picr
);
400 UNSERIALIZE_SCALAR(picInterrupting
);
404 UNSERIALIZE_SCALAR(time0when
);
405 UNSERIALIZE_SCALAR(time2when
);
406 UNSERIALIZE_SCALAR(rtcwhen
);
407 timer0
.reschedule(time0when
);
408 timer2
.reschedule(time2when
);
409 rtc
.reschedule(rtcwhen
);
412 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
414 SimObjectParam
<Tsunami
*> tsunami
;
416 SimObjectParam
<MemoryController
*> mmu
;
419 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
421 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
423 INIT_PARAM(tsunami
, "Tsunami"),
424 INIT_PARAM_DFLT(time
, "System time to use "
425 "(0 for actual time, default is 1/1/06", ULL(1136073600)),
426 INIT_PARAM(mmu
, "Memory Controller"),
427 INIT_PARAM(addr
, "Device Address")
429 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
431 CREATE_SIM_OBJECT(TsunamiIO
)
433 return new TsunamiIO(getInstanceName(), tsunami
, time
, addr
, mmu
);
436 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO
)