2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Tsunami I/O including PIC, PIT, RTC, DMA
39 #include "base/trace.hh"
40 #include "dev/tsunami_io.hh"
41 #include "dev/tsunami.hh"
42 #include "mem/bus/bus.hh"
43 #include "mem/bus/pio_interface.hh"
44 #include "mem/bus/pio_interface_impl.hh"
45 #include "sim/builder.hh"
46 #include "dev/tsunami_cchip.hh"
47 #include "dev/tsunamireg.h"
48 #include "mem/functional_mem/memory_control.hh"
52 #define UNIX_YEAR_OFFSET 52
54 // Timer Event for Periodic interrupt of RTC
55 TsunamiIO::RTCEvent::RTCEvent(Tsunami
* t
)
56 : Event(&mainEventQueue
), tsunami(t
)
58 DPRINTF(MC146818
, "RTC Event Initilizing\n");
59 schedule(curTick
+ ticksPerSecond
/RTC_RATE
);
63 TsunamiIO::RTCEvent::process()
65 DPRINTF(MC146818
, "RTC Timer Interrupt\n");
66 schedule(curTick
+ ticksPerSecond
/RTC_RATE
);
67 //Actually interrupt the processor here
68 tsunami
->cchip
->postRTC();
73 TsunamiIO::RTCEvent::description()
75 return "tsunami RTC 1024Hz interrupt";
79 TsunamiIO::RTCEvent::serialize(std::ostream
&os
)
82 SERIALIZE_SCALAR(time
);
86 TsunamiIO::RTCEvent::unserialize(Checkpoint
*cp
, const std::string
§ion
)
89 UNSERIALIZE_SCALAR(time
);
94 // Timer Event for PIT Timers
95 TsunamiIO::ClockEvent::ClockEvent()
96 : Event(&mainEventQueue
)
98 DPRINTF(Tsunami
, "Clock Event Initilizing\n");
103 TsunamiIO::ClockEvent::process()
105 DPRINTF(Tsunami
, "Timer Interrupt\n");
107 status
= 0x20; // set bit that linux is looking for
109 schedule(curTick
+ interval
);
113 TsunamiIO::ClockEvent::Program(int count
)
115 DPRINTF(Tsunami
, "Timer set to curTick + %d\n", count
);
116 // should be count * (cpufreq/pitfreq)
117 interval
= count
* ticksPerSecond
/1193180UL;
118 schedule(curTick
+ interval
);
123 TsunamiIO::ClockEvent::description()
125 return "tsunami 8254 Interval timer";
129 TsunamiIO::ClockEvent::ChangeMode(uint8_t md
)
135 TsunamiIO::ClockEvent::Status()
141 TsunamiIO::ClockEvent::serialize(std::ostream
&os
)
143 Tick time
= scheduled() ? when() : 0;
144 SERIALIZE_SCALAR(time
);
145 SERIALIZE_SCALAR(status
);
146 SERIALIZE_SCALAR(mode
);
147 SERIALIZE_SCALAR(interval
);
151 TsunamiIO::ClockEvent::unserialize(Checkpoint
*cp
, const std::string
§ion
)
154 UNSERIALIZE_SCALAR(time
);
155 UNSERIALIZE_SCALAR(status
);
156 UNSERIALIZE_SCALAR(mode
);
157 UNSERIALIZE_SCALAR(interval
);
162 TsunamiIO::TsunamiIO(const string
&name
, Tsunami
*t
, time_t init_time
,
163 Addr a
, MemoryController
*mmu
, HierParams
*hier
, Bus
*bus
,
165 : PioDevice(name
), addr(a
), tsunami(t
), rtc(t
)
167 mmu
->add_child(this, RangeSize(addr
, size
));
170 pioInterface
= newPioInterface(name
, hier
, bus
, this,
171 &TsunamiIO::cacheAccess
);
172 pioInterface
->addAddrRange(RangeSize(addr
, size
));
173 pioLatency
= pio_latency
* bus
->clockRatio
;
176 // set the back pointer from tsunami to myself
180 set_time(init_time
== 0 ? time(NULL
) : init_time
);
183 picInterrupting
= false;
187 TsunamiIO::set_time(time_t t
)
190 DPRINTFN("Real-time clock set to %s", asctime(&tm
));
194 TsunamiIO::read(MemReqPtr
&req
, uint8_t *data
)
196 DPRINTF(Tsunami
, "io read va=%#x size=%d IOPorrt=%#x\n",
197 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff);
199 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
203 case sizeof(uint8_t):
206 // !!! If this is modified 64bit case needs to be too
207 // Pal code has to do a 64 bit physical read because there is
208 // no load physical byte instruction
209 *(uint8_t*)data
= picr
;
212 // PIC2 not implemnted... just return 0
213 *(uint8_t*)data
= 0x00;
216 *(uint8_t*)data
= timer2
.Status();
220 case RTC_CONTROL_REGISTERA
:
221 *(uint8_t*)data
= uip
<< 7 | 0x26;
224 case RTC_CONTROL_REGISTERB
:
225 // DM and 24/12 and UIE
226 *(uint8_t*)data
= 0x46;
228 case RTC_CONTROL_REGISTERC
:
229 // If we want to support RTC user access in linux
230 // This won't work, but for now it's fine
231 *(uint8_t*)data
= 0x00;
233 case RTC_CONTROL_REGISTERD
:
234 panic("RTC Control Register D not implemented");
236 *(uint8_t *)data
= tm
.tm_sec
;
239 *(uint8_t *)data
= tm
.tm_min
;
242 *(uint8_t *)data
= tm
.tm_hour
;
244 case RTC_DAY_OF_WEEK
:
245 *(uint8_t *)data
= tm
.tm_wday
;
247 case RTC_DAY_OF_MONTH
:
248 *(uint8_t *)data
= tm
.tm_mday
;
250 *(uint8_t *)data
= tm
.tm_mon
+ 1;
253 *(uint8_t *)data
= tm
.tm_year
- UNIX_YEAR_OFFSET
;
256 panic("Unknown RTC Address\n");
260 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
262 case sizeof(uint16_t):
263 case sizeof(uint32_t):
264 panic("I/O Read - invalid size - va %#x size %d\n",
265 req
->vaddr
, req
->size
);
267 case sizeof(uint64_t):
270 // !!! If this is modified 8bit case needs to be too
271 // Pal code has to do a 64 bit physical read because there is
272 // no load physical byte instruction
273 *(uint64_t*)data
= (uint64_t)picr
;
276 panic("I/O Read - invalid size - va %#x size %d\n",
277 req
->vaddr
, req
->size
);
281 panic("I/O Read - invalid size - va %#x size %d\n",
282 req
->vaddr
, req
->size
);
284 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
290 TsunamiIO::write(MemReqPtr
&req
, const uint8_t *data
)
294 uint8_t dt
= *(uint8_t*)data
;
298 DPRINTF(Tsunami
, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
299 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff, dt64
);
301 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
304 case sizeof(uint8_t):
306 case TSDEV_PIC1_MASK
:
307 mask1
= ~(*(uint8_t*)data
);
308 if ((picr
& mask1
) && !picInterrupting
) {
309 picInterrupting
= true;
310 tsunami
->cchip
->postDRIR(55);
311 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
313 if ((!(picr
& mask1
)) && picInterrupting
) {
314 picInterrupting
= false;
315 tsunami
->cchip
->clearDRIR(55);
316 DPRINTF(Tsunami
, "clearing pic interrupt\n");
319 case TSDEV_PIC2_MASK
:
320 mask2
= *(uint8_t*)data
;
321 //PIC2 Not implemented to interrupt
324 // clear the interrupt on the PIC
325 picr
&= ~(1 << (*(uint8_t*)data
& 0xF));
327 tsunami
->cchip
->clearDRIR(55);
331 case TSDEV_DMA1_RESET
:
333 case TSDEV_DMA2_RESET
:
335 case TSDEV_DMA1_MODE
:
336 mode1
= *(uint8_t*)data
;
338 case TSDEV_DMA2_MODE
:
339 mode2
= *(uint8_t*)data
;
341 case TSDEV_DMA1_MASK
:
342 case TSDEV_DMA2_MASK
:
347 if ((*(uint8_t*)data
& 0x30) != 0x30)
348 panic("Only L/M write supported\n");
350 switch(*(uint8_t*)data
>> 6) {
352 timer0
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
355 timer2
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
358 panic("Read Back Command not implemented\n");
361 case TSDEV_TMR2_DATA
:
362 /* two writes before we actually start the Timer
363 so I set a flag in the timerData */
364 if(timerData
& 0x1000) {
366 timerData
+= *(uint8_t*)data
<< 8;
367 timer2
.Program(timerData
);
369 timerData
= *(uint8_t*)data
;
373 case TSDEV_TMR0_DATA
:
374 /* two writes before we actually start the Timer
375 so I set a flag in the timerData */
376 if(timerData
& 0x1000) {
378 timerData
+= *(uint8_t*)data
<< 8;
379 timer0
.Program(timerData
);
381 timerData
= *(uint8_t*)data
;
386 RTCAddress
= *(uint8_t*)data
;
389 panic("RTC Write not implmented (rtc.o won't work)\n");
391 panic("I/O Write - va%#x size %d\n", req
->vaddr
, req
->size
);
393 case sizeof(uint16_t):
394 case sizeof(uint32_t):
395 case sizeof(uint64_t):
397 panic("I/O Write - invalid size - va %#x size %d\n",
398 req
->vaddr
, req
->size
);
406 TsunamiIO::postPIC(uint8_t bitvector
)
408 //PIC2 Is not implemented, because nothing of interest there
411 tsunami
->cchip
->postDRIR(55);
412 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
417 TsunamiIO::clearPIC(uint8_t bitvector
)
419 //PIC2 Is not implemented, because nothing of interest there
421 if (!(picr
& mask1
)) {
422 tsunami
->cchip
->clearDRIR(55);
423 DPRINTF(Tsunami
, "clearing pic interrupt to cchip\n");
428 TsunamiIO::cacheAccess(MemReqPtr
&req
)
430 return curTick
+ pioLatency
;
434 TsunamiIO::serialize(std::ostream
&os
)
436 SERIALIZE_SCALAR(timerData
);
437 SERIALIZE_SCALAR(uip
);
438 SERIALIZE_SCALAR(mask1
);
439 SERIALIZE_SCALAR(mask2
);
440 SERIALIZE_SCALAR(mode1
);
441 SERIALIZE_SCALAR(mode2
);
442 SERIALIZE_SCALAR(picr
);
443 SERIALIZE_SCALAR(picInterrupting
);
444 SERIALIZE_SCALAR(RTCAddress
);
446 // Serialize the timers
447 nameOut(os
, csprintf("%s.timer0", name()));
448 timer0
.serialize(os
);
449 nameOut(os
, csprintf("%s.timer2", name()));
450 timer2
.serialize(os
);
451 nameOut(os
, csprintf("%s.rtc", name()));
456 TsunamiIO::unserialize(Checkpoint
*cp
, const std::string
§ion
)
458 UNSERIALIZE_SCALAR(timerData
);
459 UNSERIALIZE_SCALAR(uip
);
460 UNSERIALIZE_SCALAR(mask1
);
461 UNSERIALIZE_SCALAR(mask2
);
462 UNSERIALIZE_SCALAR(mode1
);
463 UNSERIALIZE_SCALAR(mode2
);
464 UNSERIALIZE_SCALAR(picr
);
465 UNSERIALIZE_SCALAR(picInterrupting
);
466 UNSERIALIZE_SCALAR(RTCAddress
);
468 // Unserialize the timers
469 timer0
.unserialize(cp
, csprintf("%s.timer0", section
));
470 timer2
.unserialize(cp
, csprintf("%s.timer2", section
));
471 rtc
.unserialize(cp
, csprintf("%s.rtc", section
));
474 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
476 SimObjectParam
<Tsunami
*> tsunami
;
478 SimObjectParam
<MemoryController
*> mmu
;
480 SimObjectParam
<Bus
*> io_bus
;
481 Param
<Tick
> pio_latency
;
482 SimObjectParam
<HierParams
*> hier
;
484 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
486 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
488 INIT_PARAM(tsunami
, "Tsunami"),
489 INIT_PARAM_DFLT(time
, "System time to use "
490 "(0 for actual time, default is 1/1/06", ULL(1136073600)),
491 INIT_PARAM(mmu
, "Memory Controller"),
492 INIT_PARAM(addr
, "Device Address"),
493 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
494 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
495 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
497 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
499 CREATE_SIM_OBJECT(TsunamiIO
)
501 return new TsunamiIO(getInstanceName(), tsunami
, time
, addr
, mmu
, hier
,
502 io_bus
, pio_latency
);
505 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO
)