2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Tsunami I/O including PIC, PIT, RTC, DMA
39 #include "base/trace.hh"
40 #include "dev/tsunami_io.hh"
41 #include "dev/tsunami.hh"
42 #include "mem/bus/bus.hh"
43 #include "mem/bus/pio_interface.hh"
44 #include "mem/bus/pio_interface_impl.hh"
45 #include "sim/builder.hh"
46 #include "dev/tsunami_cchip.hh"
47 #include "dev/tsunamireg.h"
48 #include "dev/rtcreg.h"
49 #include "mem/functional_mem/memory_control.hh"
53 #define UNIX_YEAR_OFFSET 52
55 // Timer Event for Periodic interrupt of RTC
56 TsunamiIO::RTCEvent::RTCEvent(Tsunami
* t
, Tick i
)
57 : Event(&mainEventQueue
), tsunami(t
), interval(i
)
59 DPRINTF(MC146818
, "RTC Event Initilizing\n");
60 schedule(curTick
+ interval
);
64 TsunamiIO::RTCEvent::process()
66 DPRINTF(MC146818
, "RTC Timer Interrupt\n");
67 schedule(curTick
+ interval
);
68 //Actually interrupt the processor here
69 tsunami
->cchip
->postRTC();
73 TsunamiIO::RTCEvent::description()
75 return "tsunami RTC interrupt";
79 TsunamiIO::RTCEvent::serialize(std::ostream
&os
)
82 SERIALIZE_SCALAR(time
);
86 TsunamiIO::RTCEvent::unserialize(Checkpoint
*cp
, const std::string
§ion
)
89 UNSERIALIZE_SCALAR(time
);
94 // Timer Event for PIT Timers
95 TsunamiIO::ClockEvent::ClockEvent()
96 : Event(&mainEventQueue
)
98 /* This is the PIT Tick Rate. A constant for the 8254 timer. The
99 * Tsunami platform has one of these cycle counters on the Cypress
100 * South Bridge and it is used by linux for estimating the cycle
101 * frequency of the machine it is running on. --Ali
103 interval
= (Tick
)(Clock::Float::s
/ 1193180.0);
105 DPRINTF(Tsunami
, "Clock Event Initilizing\n");
110 TsunamiIO::ClockEvent::process()
112 DPRINTF(Tsunami
, "Timer Interrupt\n");
114 status
= 0x20; // set bit that linux is looking for
116 schedule(curTick
+ interval
);
120 TsunamiIO::ClockEvent::Program(int count
)
122 DPRINTF(Tsunami
, "Timer set to curTick + %d\n", count
* interval
);
123 schedule(curTick
+ count
* interval
);
128 TsunamiIO::ClockEvent::description()
130 return "tsunami 8254 Interval timer";
134 TsunamiIO::ClockEvent::ChangeMode(uint8_t md
)
140 TsunamiIO::ClockEvent::Status()
146 TsunamiIO::ClockEvent::serialize(std::ostream
&os
)
148 Tick time
= scheduled() ? when() : 0;
149 SERIALIZE_SCALAR(time
);
150 SERIALIZE_SCALAR(status
);
151 SERIALIZE_SCALAR(mode
);
152 SERIALIZE_SCALAR(interval
);
156 TsunamiIO::ClockEvent::unserialize(Checkpoint
*cp
, const std::string
§ion
)
159 UNSERIALIZE_SCALAR(time
);
160 UNSERIALIZE_SCALAR(status
);
161 UNSERIALIZE_SCALAR(mode
);
162 UNSERIALIZE_SCALAR(interval
);
167 TsunamiIO::TsunamiIO(const string
&name
, Tsunami
*t
, time_t init_time
,
168 Addr a
, MemoryController
*mmu
, HierParams
*hier
, Bus
*bus
,
169 Tick pio_latency
, Tick ci
)
170 : PioDevice(name
, t
), addr(a
), clockInterval(ci
), tsunami(t
), rtc(t
, ci
)
172 mmu
->add_child(this, RangeSize(addr
, size
));
175 pioInterface
= newPioInterface(name
, hier
, bus
, this,
176 &TsunamiIO::cacheAccess
);
177 pioInterface
->addAddrRange(RangeSize(addr
, size
));
178 pioLatency
= pio_latency
* bus
->clockRatio
;
181 // set the back pointer from tsunami to myself
185 set_time(init_time
== 0 ? time(NULL
) : init_time
);
188 picInterrupting
= false;
192 TsunamiIO::frequency() const
194 return Clock::Frequency
/ clockInterval
;
198 TsunamiIO::set_time(time_t t
)
201 DPRINTFN("Real-time clock set to %s", asctime(&tm
));
205 TsunamiIO::read(MemReqPtr
&req
, uint8_t *data
)
207 DPRINTF(Tsunami
, "io read va=%#x size=%d IOPorrt=%#x\n",
208 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff);
210 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
214 case sizeof(uint8_t):
217 // !!! If this is modified 64bit case needs to be too
218 // Pal code has to do a 64 bit physical read because there is
219 // no load physical byte instruction
220 *(uint8_t*)data
= picr
;
223 // PIC2 not implemnted... just return 0
224 *(uint8_t*)data
= 0x00;
227 *(uint8_t*)data
= timer2
.Status();
232 *(uint8_t*)data
= uip
<< 7 | 0x26;
236 // DM and 24/12 and UIE
237 *(uint8_t*)data
= 0x46;
240 // If we want to support RTC user access in linux
241 // This won't work, but for now it's fine
242 *(uint8_t*)data
= 0x00;
245 panic("RTC Control Register D not implemented");
247 *(uint8_t *)data
= tm
.tm_sec
;
250 *(uint8_t *)data
= tm
.tm_min
;
253 *(uint8_t *)data
= tm
.tm_hour
;
256 *(uint8_t *)data
= tm
.tm_wday
;
259 *(uint8_t *)data
= tm
.tm_mday
;
261 *(uint8_t *)data
= tm
.tm_mon
+ 1;
264 *(uint8_t *)data
= tm
.tm_year
- UNIX_YEAR_OFFSET
;
267 panic("Unknown RTC Address\n");
271 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
273 case sizeof(uint16_t):
274 case sizeof(uint32_t):
275 panic("I/O Read - invalid size - va %#x size %d\n",
276 req
->vaddr
, req
->size
);
278 case sizeof(uint64_t):
281 // !!! If this is modified 8bit case needs to be too
282 // Pal code has to do a 64 bit physical read because there is
283 // no load physical byte instruction
284 *(uint64_t*)data
= (uint64_t)picr
;
287 panic("I/O Read - invalid size - va %#x size %d\n",
288 req
->vaddr
, req
->size
);
292 panic("I/O Read - invalid size - va %#x size %d\n",
293 req
->vaddr
, req
->size
);
295 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
301 TsunamiIO::write(MemReqPtr
&req
, const uint8_t *data
)
305 uint8_t dt
= *(uint8_t*)data
;
309 DPRINTF(Tsunami
, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
310 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff, dt64
);
312 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
315 case sizeof(uint8_t):
317 case TSDEV_PIC1_MASK
:
318 mask1
= ~(*(uint8_t*)data
);
319 if ((picr
& mask1
) && !picInterrupting
) {
320 picInterrupting
= true;
321 tsunami
->cchip
->postDRIR(55);
322 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
324 if ((!(picr
& mask1
)) && picInterrupting
) {
325 picInterrupting
= false;
326 tsunami
->cchip
->clearDRIR(55);
327 DPRINTF(Tsunami
, "clearing pic interrupt\n");
330 case TSDEV_PIC2_MASK
:
331 mask2
= *(uint8_t*)data
;
332 //PIC2 Not implemented to interrupt
335 // clear the interrupt on the PIC
336 picr
&= ~(1 << (*(uint8_t*)data
& 0xF));
338 tsunami
->cchip
->clearDRIR(55);
342 case TSDEV_DMA1_RESET
:
344 case TSDEV_DMA2_RESET
:
346 case TSDEV_DMA1_MODE
:
347 mode1
= *(uint8_t*)data
;
349 case TSDEV_DMA2_MODE
:
350 mode2
= *(uint8_t*)data
;
352 case TSDEV_DMA1_MASK
:
353 case TSDEV_DMA2_MASK
:
358 if ((*(uint8_t*)data
& 0x30) != 0x30)
359 panic("Only L/M write supported\n");
361 switch(*(uint8_t*)data
>> 6) {
363 timer0
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
366 timer2
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
369 panic("Read Back Command not implemented\n");
372 case TSDEV_TMR2_DATA
:
373 /* two writes before we actually start the Timer
374 so I set a flag in the timerData */
375 if(timerData
& 0x1000) {
377 timerData
+= *(uint8_t*)data
<< 8;
378 timer2
.Program(timerData
);
380 timerData
= *(uint8_t*)data
;
384 case TSDEV_TMR0_DATA
:
385 /* two writes before we actually start the Timer
386 so I set a flag in the timerData */
387 if(timerData
& 0x1000) {
389 timerData
+= *(uint8_t*)data
<< 8;
390 timer0
.Program(timerData
);
392 timerData
= *(uint8_t*)data
;
397 RTCAddress
= *(uint8_t*)data
;
400 panic("RTC Write not implmented (rtc.o won't work)\n");
402 panic("I/O Write - va%#x size %d\n", req
->vaddr
, req
->size
);
404 case sizeof(uint16_t):
405 case sizeof(uint32_t):
406 case sizeof(uint64_t):
408 panic("I/O Write - invalid size - va %#x size %d\n",
409 req
->vaddr
, req
->size
);
417 TsunamiIO::postPIC(uint8_t bitvector
)
419 //PIC2 Is not implemented, because nothing of interest there
422 tsunami
->cchip
->postDRIR(55);
423 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
428 TsunamiIO::clearPIC(uint8_t bitvector
)
430 //PIC2 Is not implemented, because nothing of interest there
432 if (!(picr
& mask1
)) {
433 tsunami
->cchip
->clearDRIR(55);
434 DPRINTF(Tsunami
, "clearing pic interrupt to cchip\n");
439 TsunamiIO::cacheAccess(MemReqPtr
&req
)
441 return curTick
+ pioLatency
;
445 TsunamiIO::serialize(std::ostream
&os
)
447 SERIALIZE_SCALAR(timerData
);
448 SERIALIZE_SCALAR(uip
);
449 SERIALIZE_SCALAR(mask1
);
450 SERIALIZE_SCALAR(mask2
);
451 SERIALIZE_SCALAR(mode1
);
452 SERIALIZE_SCALAR(mode2
);
453 SERIALIZE_SCALAR(picr
);
454 SERIALIZE_SCALAR(picInterrupting
);
455 SERIALIZE_SCALAR(RTCAddress
);
457 // Serialize the timers
458 nameOut(os
, csprintf("%s.timer0", name()));
459 timer0
.serialize(os
);
460 nameOut(os
, csprintf("%s.timer2", name()));
461 timer2
.serialize(os
);
462 nameOut(os
, csprintf("%s.rtc", name()));
467 TsunamiIO::unserialize(Checkpoint
*cp
, const std::string
§ion
)
469 UNSERIALIZE_SCALAR(timerData
);
470 UNSERIALIZE_SCALAR(uip
);
471 UNSERIALIZE_SCALAR(mask1
);
472 UNSERIALIZE_SCALAR(mask2
);
473 UNSERIALIZE_SCALAR(mode1
);
474 UNSERIALIZE_SCALAR(mode2
);
475 UNSERIALIZE_SCALAR(picr
);
476 UNSERIALIZE_SCALAR(picInterrupting
);
477 UNSERIALIZE_SCALAR(RTCAddress
);
479 // Unserialize the timers
480 timer0
.unserialize(cp
, csprintf("%s.timer0", section
));
481 timer2
.unserialize(cp
, csprintf("%s.timer2", section
));
482 rtc
.unserialize(cp
, csprintf("%s.rtc", section
));
485 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
487 SimObjectParam
<Tsunami
*> tsunami
;
489 SimObjectParam
<MemoryController
*> mmu
;
491 SimObjectParam
<Bus
*> io_bus
;
492 Param
<Tick
> pio_latency
;
493 SimObjectParam
<HierParams
*> hier
;
494 Param
<Tick
> frequency
;
496 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
498 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
500 INIT_PARAM(tsunami
, "Tsunami"),
501 INIT_PARAM(time
, "System time to use (0 for actual time"),
502 INIT_PARAM(mmu
, "Memory Controller"),
503 INIT_PARAM(addr
, "Device Address"),
504 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
505 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
506 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
),
507 INIT_PARAM(frequency
, "clock interrupt frequency")
509 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
511 CREATE_SIM_OBJECT(TsunamiIO
)
513 return new TsunamiIO(getInstanceName(), tsunami
, time
, addr
, mmu
, hier
,
514 io_bus
, pio_latency
, frequency
);
517 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO
)