2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Tsunami I/O including PIC, PIT, RTC, DMA
39 #include "base/trace.hh"
40 #include "cpu/exec_context.hh"
41 #include "dev/console.hh"
42 #include "dev/tlaser_clock.hh"
43 #include "dev/tsunami_io.hh"
44 #include "dev/tsunamireg.h"
45 #include "dev/tsunami.hh"
46 #include "mem/functional_mem/memory_control.hh"
47 #include "sim/builder.hh"
48 #include "dev/tsunami_cchip.hh"
52 #define UNIX_YEAR_OFFSET 52
54 // Timer Event for Periodic interrupt of RTC
55 TsunamiIO::RTCEvent::RTCEvent(Tsunami
* t
)
56 : Event(&mainEventQueue
), tsunami(t
)
58 DPRINTF(MC146818
, "RTC Event Initilizing\n");
59 schedule(curTick
+ ticksPerSecond
/RTC_RATE
);
63 TsunamiIO::RTCEvent::process()
65 DPRINTF(MC146818
, "RTC Timer Interrupt\n");
66 schedule(curTick
+ ticksPerSecond
/RTC_RATE
);
67 //Actually interrupt the processor here
68 tsunami
->cchip
->postRTC();
73 TsunamiIO::RTCEvent::description()
75 return "tsunami RTC 1024Hz interrupt";
78 // Timer Event for PIT Timers
79 TsunamiIO::ClockEvent::ClockEvent()
80 : Event(&mainEventQueue
)
82 DPRINTF(Tsunami
, "Clock Event Initilizing\n");
87 TsunamiIO::ClockEvent::process()
89 DPRINTF(Tsunami
, "Timer Interrupt\n");
91 status
= 0x20; // set bit that linux is looking for
93 schedule(curTick
+ interval
);
97 TsunamiIO::ClockEvent::Program(int count
)
99 DPRINTF(Tsunami
, "Timer set to curTick + %d\n", count
);
100 // should be count * (cpufreq/pitfreq)
101 interval
= count
* ticksPerSecond
/1193180UL;
102 schedule(curTick
+ interval
);
107 TsunamiIO::ClockEvent::description()
109 return "tsunami 8254 Interval timer";
113 TsunamiIO::ClockEvent::ChangeMode(uint8_t md
)
119 TsunamiIO::ClockEvent::Status()
124 TsunamiIO::TsunamiIO(const string
&name
, Tsunami
*t
, time_t init_time
,
125 Addr a
, MemoryController
*mmu
)
126 : FunctionalMemory(name
), addr(a
), tsunami(t
), rtc(t
)
128 mmu
->add_child(this, Range
<Addr
>(addr
, addr
+ size
));
130 // set the back pointer from tsunami to myself
134 set_time(init_time
== 0 ? time(NULL
) : init_time
);
137 picInterrupting
= false;
141 TsunamiIO::set_time(time_t t
)
144 DPRINTFN("Real-time clock set to %s", asctime(&tm
));
148 TsunamiIO::read(MemReqPtr
&req
, uint8_t *data
)
150 DPRINTF(Tsunami
, "io read va=%#x size=%d IOPorrt=%#x\n",
151 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff);
153 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
));
154 // ExecContext *xc = req->xc;
155 // int cpuid = xc->cpu_id;
158 case sizeof(uint8_t):
161 *(uint8_t*)data
= timer2
.Status();
165 case RTC_CONTROL_REGISTERA
:
166 *(uint8_t*)data
= uip
<< 7 | 0x26;
169 case RTC_CONTROL_REGISTERB
:
170 // DM and 24/12 and UIE
171 *(uint8_t*)data
= 0x46;
173 case RTC_CONTROL_REGISTERC
:
174 // If we want to support RTC user access in linux
175 // This won't work, but for now it's fine
176 *(uint8_t*)data
= 0x00;
178 case RTC_CONTROL_REGISTERD
:
179 panic("RTC Control Register D not implemented");
181 *(uint8_t *)data
= tm
.tm_sec
;
184 *(uint8_t *)data
= tm
.tm_min
;
187 *(uint8_t *)data
= tm
.tm_hour
;
189 case RTC_DAY_OF_WEEK
:
190 *(uint8_t *)data
= tm
.tm_wday
;
192 case RTC_DAY_OF_MONTH
:
193 *(uint8_t *)data
= tm
.tm_mday
;
195 *(uint8_t *)data
= tm
.tm_mon
+ 1;
198 *(uint8_t *)data
= tm
.tm_year
- UNIX_YEAR_OFFSET
;
201 panic("Unknown RTC Address\n");
205 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
207 case sizeof(uint16_t):
208 case sizeof(uint32_t):
209 case sizeof(uint64_t):
211 panic("I/O Read - invalid size - va %#x size %d\n",
212 req
->vaddr
, req
->size
);
214 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
220 TsunamiIO::write(MemReqPtr
&req
, const uint8_t *data
)
222 uint8_t dt
= *(uint8_t*)data
;
225 DPRINTF(Tsunami
, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
226 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff, dt64
);
228 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
));
231 case sizeof(uint8_t):
233 case TSDEV_PIC1_MASK
:
234 mask1
= *(uint8_t*)data
;
235 if ((picr
& mask1
) && !picInterrupting
) {
236 picInterrupting
= true;
237 tsunami
->cchip
->postDRIR(55);
238 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
241 case TSDEV_PIC2_MASK
:
242 mask2
= *(uint8_t*)data
;
243 //PIC2 Not implemented to interrupt
245 case TSDEV_DMA1_RESET
:
247 case TSDEV_DMA2_RESET
:
249 case TSDEV_DMA1_MODE
:
250 mode1
= *(uint8_t*)data
;
252 case TSDEV_DMA2_MODE
:
253 mode2
= *(uint8_t*)data
;
255 case TSDEV_DMA1_MASK
:
256 case TSDEV_DMA2_MASK
:
261 if ((*(uint8_t*)data
& 0x30) != 0x30)
262 panic("Only L/M write supported\n");
264 switch(*(uint8_t*)data
>> 6) {
266 timer0
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
269 timer2
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
272 panic("Read Back Command not implemented\n");
275 case TSDEV_TMR2_DATA
:
276 /* two writes before we actually start the Timer
277 so I set a flag in the timerData */
278 if(timerData
& 0x1000) {
280 timerData
+= *(uint8_t*)data
<< 8;
281 timer2
.Program(timerData
);
283 timerData
= *(uint8_t*)data
;
287 case TSDEV_TMR0_DATA
:
288 /* two writes before we actually start the Timer
289 so I set a flag in the timerData */
290 if(timerData
& 0x1000) {
292 timerData
+= *(uint8_t*)data
<< 8;
293 timer0
.Program(timerData
);
295 timerData
= *(uint8_t*)data
;
300 RTCAddress
= *(uint8_t*)data
;
303 panic("RTC Write not implmented (rtc.o won't work)\n");
305 panic("I/O Write - va%#x size %d\n", req
->vaddr
, req
->size
);
307 case sizeof(uint16_t):
308 case sizeof(uint32_t):
309 case sizeof(uint64_t):
311 panic("I/O Write - invalid size - va %#x size %d\n",
312 req
->vaddr
, req
->size
);
320 TsunamiIO::postPIC(uint8_t bitvector
)
322 //PIC2 Is not implemented, because nothing of interest there
324 if ((picr
& mask1
) && !picInterrupting
) {
325 picInterrupting
= true;
326 tsunami
->cchip
->postDRIR(55);
327 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
332 TsunamiIO::clearPIC(uint8_t bitvector
)
334 //PIC2 Is not implemented, because nothing of interest there
336 if (!(picr
& mask1
)) {
337 picInterrupting
= false;
338 tsunami
->cchip
->clearDRIR(55);
339 DPRINTF(Tsunami
, "clearing pic interrupt to cchip\n");
344 TsunamiIO::serialize(std::ostream
&os
)
346 SERIALIZE_SCALAR(timerData
);
347 SERIALIZE_SCALAR(uip
);
348 SERIALIZE_SCALAR(picr
);
349 SERIALIZE_SCALAR(picInterrupting
);
350 Tick time0when
= timer0
.when();
351 Tick time2when
= timer2
.when();
352 Tick rtcwhen
= rtc
.when();
353 SERIALIZE_SCALAR(time0when
);
354 SERIALIZE_SCALAR(time2when
);
355 SERIALIZE_SCALAR(rtcwhen
);
360 TsunamiIO::unserialize(Checkpoint
*cp
, const std::string
§ion
)
362 UNSERIALIZE_SCALAR(timerData
);
363 UNSERIALIZE_SCALAR(uip
);
364 UNSERIALIZE_SCALAR(picr
);
365 UNSERIALIZE_SCALAR(picInterrupting
);
369 UNSERIALIZE_SCALAR(time0when
);
370 UNSERIALIZE_SCALAR(time2when
);
371 UNSERIALIZE_SCALAR(rtcwhen
);
372 timer0
.reschedule(time0when
);
373 timer2
.reschedule(time2when
);
374 rtc
.reschedule(rtcwhen
);
377 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
379 SimObjectParam
<Tsunami
*> tsunami
;
381 SimObjectParam
<MemoryController
*> mmu
;
384 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
386 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
388 INIT_PARAM(tsunami
, "Tsunami"),
389 INIT_PARAM_DFLT(time
, "System time to use "
390 "(0 for actual time, default is 1/1/06", ULL(1136073600)),
391 INIT_PARAM(mmu
, "Memory Controller"),
392 INIT_PARAM(addr
, "Device Address")
394 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
396 CREATE_SIM_OBJECT(TsunamiIO
)
398 return new TsunamiIO(getInstanceName(), tsunami
, time
, addr
, mmu
);
401 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO
)