dev/tsunami_io.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Tsunami I/O including PIC, PIT, RTC, DMA
  31  */
  32
  33 #include <sys/time.h>
  34
  35 #include <deque>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "base/trace.hh"
  40 #include "dev/tsunami_io.hh"
  41 #include "dev/tsunami.hh"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/pio_interface.hh"
  44 #include "mem/bus/pio_interface_impl.hh"
  45 #include "sim/builder.hh"
  46 #include "dev/tsunami_cchip.hh"
  47 #include "dev/tsunamireg.h"
  48 #include "dev/rtcreg.h"
  49 #include "mem/functional/memory_control.hh"
  50
  51 using namespace std;
  52
  53 #define UNIX_YEAR_OFFSET 52
  54
  55 struct tm TsunamiIO::tm = { 0 };
  56
  57 // Timer Event for Periodic interrupt of RTC
  58 TsunamiIO::RTCEvent::RTCEvent(Tsunami* t, Tick i)
  59     : Event(&mainEventQueue), tsunami(t), interval(i)
  60 {
  61     DPRINTF(MC146818, "RTC Event Initilizing\n");
  62     intr_count = 0;
  63     schedule(curTick + interval);
  64 }
  65
  66 void
  67 TsunamiIO::RTCEvent::process()
  68 {
  69     DPRINTF(MC146818, "RTC Timer Interrupt\n");
  70     schedule(curTick + interval);
  71     //Actually interrupt the processor here
  72     tsunami->cchip->postRTC();
  73
  74     if (intr_count == 1023)
  75         tm.tm_sec = (tm.tm_sec + 1) % 60;
  76
  77     intr_count = (intr_count + 1) % 1024;
  78
  79 }
  80
  81 const char *
  82 TsunamiIO::RTCEvent::description()
  83 {
  84     return "tsunami RTC interrupt";
  85 }
  86
  87 void
  88 TsunamiIO::RTCEvent::serialize(std::ostream &os)
  89 {
  90     Tick time = when();
  91     SERIALIZE_SCALAR(time);
  92 }
  93
  94 void
  95 TsunamiIO::RTCEvent::unserialize(Checkpoint *cp, const std::string &section)
  96 {
  97     Tick time;
  98     UNSERIALIZE_SCALAR(time);
  99     reschedule(time);
 100 }
 101
 102
 103 // Timer Event for PIT Timers
 104 TsunamiIO::ClockEvent::ClockEvent()
 105     : Event(&mainEventQueue)
 106 {
 107     /* This is the PIT Tick Rate. A constant for the 8254 timer. The
 108      * Tsunami platform has one of these cycle counters on the Cypress
 109      * South Bridge and it is used by linux for estimating the cycle
 110      * frequency of the machine it is running on. --Ali
 111      */
 112     interval = (Tick)(Clock::Float::s / 1193180.0);
 113
 114     DPRINTF(Tsunami, "Clock Event Initilizing\n");
 115     mode = 0;
 116
 117     current_count = 0;
 118     latched_count = 0;
 119     latch_on = false;
 120     read_byte = READ_LSB;
 121 }
 122
 123 void
 124 TsunamiIO::ClockEvent::process()
 125 {
 126     DPRINTF(Tsunami, "Timer Interrupt\n");
 127     if (mode == 0)
 128         status = 0x20; // set bit that linux is looking for
 129     else
 130         schedule(curTick + interval);
 131
 132     current_count--; //decrement count
 133 }
 134
 135 void
 136 TsunamiIO::ClockEvent::Program(int count)
 137 {
 138     DPRINTF(Tsunami, "Timer set to curTick + %d\n", count * interval);
 139     schedule(curTick + count * interval);
 140     status = 0;
 141
 142     current_count = (uint16_t)count;
 143 }
 144
 145 const char *
 146 TsunamiIO::ClockEvent::description()
 147 {
 148     return "tsunami 8254 Interval timer";
 149 }
 150
 151 void
 152 TsunamiIO::ClockEvent::ChangeMode(uint8_t md)
 153 {
 154     mode = md;
 155 }
 156
 157 uint8_t
 158 TsunamiIO::ClockEvent::Status()
 159 {
 160     return status;
 161 }
 162
 163 void
 164 TsunamiIO::ClockEvent::LatchCount()
 165 {
 166     // behave like a real latch
 167     if(!latch_on) {
 168         latch_on = true;
 169         read_byte = READ_LSB;
 170         latched_count = current_count;
 171     }
 172 }
 173
 174 uint8_t
 175 TsunamiIO::ClockEvent::Read()
 176 {
 177    uint8_t result = 0;
 178
 179     if(latch_on) {
 180         switch (read_byte) {
 181           case READ_LSB:
 182             read_byte = READ_MSB;
 183             result = (uint8_t)latched_count;
 184             break;
 185           case READ_MSB:
 186             read_byte = READ_LSB;
 187             latch_on = false;
 188             result = latched_count >> 8;
 189             break;
 190         }
 191     } else {
 192         switch (read_byte) {
 193           case READ_LSB:
 194             read_byte = READ_MSB;
 195             result = (uint8_t)current_count;
 196             break;
 197           case READ_MSB:
 198             read_byte = READ_LSB;
 199             result = current_count >> 8;
 200             break;
 201         }
 202     }
 203
 204     return result;
 205 }
 206
 207
 208 void
 209 TsunamiIO::ClockEvent::serialize(std::ostream &os)
 210 {
 211     Tick time = scheduled() ? when() : 0;
 212     SERIALIZE_SCALAR(time);
 213     SERIALIZE_SCALAR(status);
 214     SERIALIZE_SCALAR(mode);
 215     SERIALIZE_SCALAR(interval);
 216 }
 217
 218 void
 219 TsunamiIO::ClockEvent::unserialize(Checkpoint *cp, const std::string &section)
 220 {
 221     Tick time;
 222     UNSERIALIZE_SCALAR(time);
 223     UNSERIALIZE_SCALAR(status);
 224     UNSERIALIZE_SCALAR(mode);
 225     UNSERIALIZE_SCALAR(interval);
 226     if (time)
 227         schedule(time);
 228 }
 229
 230 TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
 231                      Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
 232                      Tick pio_latency, Tick ci)
 233     : PioDevice(name, t), addr(a), clockInterval(ci), tsunami(t), rtc(t, ci)
 234 {
 235     mmu->add_child(this, RangeSize(addr, size));
 236
 237     if (bus) {
 238         pioInterface = newPioInterface(name, hier, bus, this,
 239                                        &TsunamiIO::cacheAccess);
 240         pioInterface->addAddrRange(RangeSize(addr, size));
 241         pioLatency = pio_latency * bus->clockRate;
 242     }
 243
 244     // set the back pointer from tsunami to myself
 245     tsunami->io = this;
 246
 247     timerData = 0;
 248     set_time(init_time == 0 ? time(NULL) : init_time);
 249     uip = 1;
 250     picr = 0;
 251     picInterrupting = false;
 252 }
 253
 254 Tick
 255 TsunamiIO::frequency() const
 256 {
 257     return Clock::Frequency / clockInterval;
 258 }
 259
 260 void
 261 TsunamiIO::set_time(time_t t)
 262 {
 263     gmtime_r(&t, &tm);
 264     DPRINTFN("Real-time clock set to %s", asctime(&tm));
 265 }
 266
 267 Fault
 268 TsunamiIO::read(MemReqPtr &req, uint8_t *data)
 269 {
 270     DPRINTF(Tsunami, "io read  va=%#x size=%d IOPorrt=%#x\n",
 271             req->vaddr, req->size, req->vaddr & 0xfff);
 272
 273     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) + 0x20;
 274
 275
 276     switch(req->size) {
 277       case sizeof(uint8_t):
 278         switch(daddr) {
 279           // PIC1 mask read
 280           case TSDEV_PIC1_MASK:
 281             *(uint8_t*)data = ~mask1;
 282             return No_Fault;
 283           case TSDEV_PIC2_MASK:
 284             *(uint8_t*)data = ~mask2;
 285             return No_Fault;
 286           case TSDEV_PIC1_ISR:
 287               // !!! If this is modified 64bit case needs to be too
 288               // Pal code has to do a 64 bit physical read because there is
 289               // no load physical byte instruction
 290               *(uint8_t*)data = picr;
 291               return No_Fault;
 292           case TSDEV_PIC2_ISR:
 293               // PIC2 not implemnted... just return 0
 294               *(uint8_t*)data = 0x00;
 295               return No_Fault;
 296           case TSDEV_TMR_CTL:
 297             *(uint8_t*)data = timer2.Status();
 298             return No_Fault;
 299           case TSDEV_TMR0_DATA:
 300             *(uint8_t *)data = timer0.Read();
 301             return No_Fault;
 302           case TSDEV_RTC_DATA:
 303             switch(RTCAddress) {
 304               case RTC_CNTRL_REGA:
 305                 *(uint8_t*)data = uip << 7 | 0x26;
 306                 uip = !uip;
 307                 return No_Fault;
 308               case RTC_CNTRL_REGB:
 309                 // DM and 24/12 and UIE
 310                 *(uint8_t*)data = 0x46;
 311                 return No_Fault;
 312               case RTC_CNTRL_REGC:
 313                 // If we want to support RTC user access in linux
 314                 // This won't work, but for now it's fine
 315                 *(uint8_t*)data = 0x00;
 316                 return No_Fault;
 317               case RTC_CNTRL_REGD:
 318                 panic("RTC Control Register D not implemented");
 319               case RTC_SEC:
 320                 *(uint8_t *)data = tm.tm_sec;
 321                 return No_Fault;
 322               case RTC_MIN:
 323                 *(uint8_t *)data = tm.tm_min;
 324                 return No_Fault;
 325               case RTC_HR:
 326                 *(uint8_t *)data = tm.tm_hour;
 327                 return No_Fault;
 328               case RTC_DOW:
 329                 *(uint8_t *)data = tm.tm_wday;
 330                 return No_Fault;
 331               case RTC_DOM:
 332                 *(uint8_t *)data = tm.tm_mday;
 333                 return No_Fault;
 334               case RTC_MON:
 335                 *(uint8_t *)data = tm.tm_mon + 1;
 336                 return No_Fault;
 337               case RTC_YEAR:
 338                 *(uint8_t *)data = tm.tm_year - UNIX_YEAR_OFFSET;
 339                 return No_Fault;
 340               default:
 341                 panic("Unknown RTC Address\n");
 342             }
 343
 344           /* Added for keyboard reads */
 345           case TSDEV_KBD:
 346             *(uint8_t *)data = 0x00;
 347             return No_Fault;
 348           /* Added for ATA PCI DMA */
 349           case ATA_PCI_DMA:
 350             *(uint8_t *)data = 0x00;
 351             return No_Fault;
 352           default:
 353             panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
 354         }
 355       case sizeof(uint16_t):
 356       case sizeof(uint32_t):
 357         panic("I/O Read - invalid size - va %#x size %d\n",
 358               req->vaddr, req->size);
 359
 360       case sizeof(uint64_t):
 361        switch(daddr) {
 362           case TSDEV_PIC1_ISR:
 363               // !!! If this is modified 8bit case needs to be too
 364               // Pal code has to do a 64 bit physical read because there is
 365               // no load physical byte instruction
 366               *(uint64_t*)data = (uint64_t)picr;
 367               return No_Fault;
 368           default:
 369               panic("I/O Read - invalid size - va %#x size %d\n",
 370                     req->vaddr, req->size);
 371        }
 372
 373       default:
 374         panic("I/O Read - invalid size - va %#x size %d\n",
 375               req->vaddr, req->size);
 376     }
 377     panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
 378
 379     return No_Fault;
 380 }
 381
 382 Fault
 383 TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
 384 {
 385
 386 #if TRACING_ON
 387     uint8_t dt = *(uint8_t*)data;
 388     uint64_t dt64 = dt;
 389 #endif
 390
 391     DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
 392             req->vaddr, req->size, req->vaddr & 0xfff, dt64);
 393
 394     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) + 0x20;
 395
 396     switch(req->size) {
 397       case sizeof(uint8_t):
 398         switch(daddr) {
 399           case TSDEV_PIC1_MASK:
 400             mask1 = ~(*(uint8_t*)data);
 401             if ((picr & mask1) && !picInterrupting) {
 402                 picInterrupting = true;
 403                 tsunami->cchip->postDRIR(55);
 404                 DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
 405             }
 406             if ((!(picr & mask1)) && picInterrupting) {
 407                 picInterrupting = false;
 408                 tsunami->cchip->clearDRIR(55);
 409                 DPRINTF(Tsunami, "clearing pic interrupt\n");
 410             }
 411             return No_Fault;
 412           case TSDEV_PIC2_MASK:
 413             mask2 = *(uint8_t*)data;
 414             //PIC2 Not implemented to interrupt
 415             return No_Fault;
 416           case TSDEV_PIC1_ACK:
 417             // clear the interrupt on the PIC
 418             picr &= ~(1 << (*(uint8_t*)data & 0xF));
 419             if (!(picr & mask1))
 420                 tsunami->cchip->clearDRIR(55);
 421             return No_Fault;
 422           case TSDEV_PIC2_ACK:
 423             return No_Fault;
 424           case TSDEV_DMA1_RESET:
 425             return No_Fault;
 426           case TSDEV_DMA2_RESET:
 427             return No_Fault;
 428           case TSDEV_DMA1_MODE:
 429             mode1 = *(uint8_t*)data;
 430             return No_Fault;
 431           case TSDEV_DMA2_MODE:
 432             mode2 = *(uint8_t*)data;
 433             return No_Fault;
 434           case TSDEV_DMA1_MASK:
 435           case TSDEV_DMA2_MASK:
 436             return No_Fault;
 437           case TSDEV_TMR_CTL:
 438             return No_Fault;
 439           case TSDEV_TMR2_CTL:
 440             switch((*(uint8_t*)data >> 4) & 0x3) {
 441               case 0x0:
 442                 switch(*(uint8_t*)data >> 6) {
 443                   case 0:
 444                     timer0.LatchCount();
 445                     break;
 446                   case 2:
 447                     timer2.LatchCount();
 448                     break;
 449                   default:
 450                     panic("Read Back Command not implemented\n");
 451                 }
 452                 break;
 453               case 0x3:
 454                 break;
 455               default:
 456                 panic("Only L/M write and Counter-Latch read supported\n");
 457             }
 458
 459             switch(*(uint8_t*)data >> 6) {
 460               case 0:
 461                 timer0.ChangeMode((*(uint8_t*)data & 0xF) >> 1);
 462                 break;
 463               case 2:
 464                 timer2.ChangeMode((*(uint8_t*)data & 0xF) >> 1);
 465                 break;
 466               default:
 467                 panic("Read Back Command not implemented\n");
 468             }
 469             return No_Fault;
 470           case TSDEV_TMR2_DATA:
 471             /* two writes before we actually start the Timer
 472                so I set a flag in the timerData */
 473             if(timerData & 0x1000) {
 474                 timerData &= 0x1000;
 475                 timerData += *(uint8_t*)data << 8;
 476                 timer2.Program(timerData);
 477             } else {
 478                 timerData = *(uint8_t*)data;
 479                 timerData |= 0x1000;
 480             }
 481             return No_Fault;
 482           case TSDEV_TMR0_DATA:
 483             /* two writes before we actually start the Timer
 484                so I set a flag in the timerData */
 485             if(timerData & 0x1000) {
 486                 timerData &= 0x1000;
 487                 timerData += *(uint8_t*)data << 8;
 488                 timer0.Program(timerData);
 489             } else {
 490                 timerData = *(uint8_t*)data;
 491                 timerData |= 0x1000;
 492             }
 493             return No_Fault;
 494           case TSDEV_RTC_ADDR:
 495             RTCAddress = *(uint8_t*)data;
 496             return No_Fault;
 497           case TSDEV_KBD:
 498             return No_Fault;
 499           case TSDEV_RTC_DATA:
 500             switch(RTCAddress) {
 501               case RTC_CNTRL_REGA:
 502                 return No_Fault;
 503               case RTC_CNTRL_REGB:
 504                 return No_Fault;
 505               case RTC_CNTRL_REGC:
 506                 return No_Fault;
 507               case RTC_CNTRL_REGD:
 508                 return No_Fault;
 509               case RTC_SEC:
 510                 tm.tm_sec = *(uint8_t *)data;
 511                 return No_Fault;
 512               case RTC_MIN:
 513                 tm.tm_min = *(uint8_t *)data;
 514                 return No_Fault;
 515               case RTC_HR:
 516                 tm.tm_hour = *(uint8_t *)data;
 517                 return No_Fault;
 518               case RTC_DOW:
 519                 tm.tm_wday = *(uint8_t *)data;
 520                 return No_Fault;
 521               case RTC_DOM:
 522                 tm.tm_mday = *(uint8_t *)data;
 523                 return No_Fault;
 524               case RTC_MON:
 525                  tm.tm_mon = *(uint8_t *)data - 1;
 526                 return No_Fault;
 527               case RTC_YEAR:
 528                 tm.tm_year = *(uint8_t *)data + UNIX_YEAR_OFFSET;
 529                 return No_Fault;
 530             //panic("RTC Write not implmented (rtc.o won't work)\n");
 531             }
 532           default:
 533             panic("I/O Write - va%#x size %d\n", req->vaddr, req->size);
 534         }
 535       case sizeof(uint16_t):
 536       case sizeof(uint32_t):
 537       case sizeof(uint64_t):
 538       default:
 539         panic("I/O Write - invalid size - va %#x size %d\n",
 540               req->vaddr, req->size);
 541     }
 542
 543
 544     return No_Fault;
 545 }
 546
 547 void
 548 TsunamiIO::postPIC(uint8_t bitvector)
 549 {
 550     //PIC2 Is not implemented, because nothing of interest there
 551     picr |= bitvector;
 552     if (picr & mask1) {
 553         tsunami->cchip->postDRIR(55);
 554         DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
 555     }
 556 }
 557
 558 void
 559 TsunamiIO::clearPIC(uint8_t bitvector)
 560 {
 561     //PIC2 Is not implemented, because nothing of interest there
 562     picr &= ~bitvector;
 563     if (!(picr & mask1)) {
 564         tsunami->cchip->clearDRIR(55);
 565         DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
 566     }
 567 }
 568
 569 Tick
 570 TsunamiIO::cacheAccess(MemReqPtr &req)
 571 {
 572     return curTick + pioLatency;
 573 }
 574
 575 void
 576 TsunamiIO::serialize(std::ostream &os)
 577 {
 578     SERIALIZE_SCALAR(timerData);
 579     SERIALIZE_SCALAR(uip);
 580     SERIALIZE_SCALAR(mask1);
 581     SERIALIZE_SCALAR(mask2);
 582     SERIALIZE_SCALAR(mode1);
 583     SERIALIZE_SCALAR(mode2);
 584     SERIALIZE_SCALAR(picr);
 585     SERIALIZE_SCALAR(picInterrupting);
 586     SERIALIZE_SCALAR(RTCAddress);
 587
 588     // Serialize the timers
 589     nameOut(os, csprintf("%s.timer0", name()));
 590     timer0.serialize(os);
 591     nameOut(os, csprintf("%s.timer2", name()));
 592     timer2.serialize(os);
 593     nameOut(os, csprintf("%s.rtc", name()));
 594     rtc.serialize(os);
 595 }
 596
 597 void
 598 TsunamiIO::unserialize(Checkpoint *cp, const std::string &section)
 599 {
 600     UNSERIALIZE_SCALAR(timerData);
 601     UNSERIALIZE_SCALAR(uip);
 602     UNSERIALIZE_SCALAR(mask1);
 603     UNSERIALIZE_SCALAR(mask2);
 604     UNSERIALIZE_SCALAR(mode1);
 605     UNSERIALIZE_SCALAR(mode2);
 606     UNSERIALIZE_SCALAR(picr);
 607     UNSERIALIZE_SCALAR(picInterrupting);
 608     UNSERIALIZE_SCALAR(RTCAddress);
 609
 610     // Unserialize the timers
 611     timer0.unserialize(cp, csprintf("%s.timer0", section));
 612     timer2.unserialize(cp, csprintf("%s.timer2", section));
 613     rtc.unserialize(cp, csprintf("%s.rtc", section));
 614 }
 615
 616 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
 617
 618     SimObjectParam<Tsunami *> tsunami;
 619     Param<time_t> time;
 620     SimObjectParam<MemoryController *> mmu;
 621     Param<Addr> addr;
 622     SimObjectParam<Bus*> io_bus;
 623     Param<Tick> pio_latency;
 624     SimObjectParam<HierParams *> hier;
 625     Param<Tick> frequency;
 626
 627 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
 628
 629 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
 630
 631     INIT_PARAM(tsunami, "Tsunami"),
 632     INIT_PARAM(time, "System time to use (0 for actual time"),
 633     INIT_PARAM(mmu, "Memory Controller"),
 634     INIT_PARAM(addr, "Device Address"),
 635     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
 636     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 637     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
 638     INIT_PARAM(frequency, "clock interrupt frequency")
 639
 640 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
 641
 642 CREATE_SIM_OBJECT(TsunamiIO)
 643 {
 644     return new TsunamiIO(getInstanceName(), tsunami, time,  addr, mmu, hier,
 645                          io_bus, pio_latency, frequency);
 646 }
 647
 648 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)