2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Tsunami I/O including PIC, PIT, RTC, DMA
39 #include "base/trace.hh"
40 #include "dev/tsunami_io.hh"
41 #include "dev/tsunami.hh"
42 #include "mem/bus/bus.hh"
43 #include "mem/bus/pio_interface.hh"
44 #include "mem/bus/pio_interface_impl.hh"
45 #include "sim/builder.hh"
46 #include "dev/tsunami_cchip.hh"
47 #include "dev/tsunamireg.h"
48 #include "dev/rtcreg.h"
49 #include "mem/functional/memory_control.hh"
53 #define UNIX_YEAR_OFFSET 52
55 struct tm
TsunamiIO::tm
= { 0 };
57 // Timer Event for Periodic interrupt of RTC
58 TsunamiIO::RTCEvent::RTCEvent(Tsunami
* t
, Tick i
)
59 : Event(&mainEventQueue
), tsunami(t
), interval(i
)
61 DPRINTF(MC146818
, "RTC Event Initilizing\n");
62 schedule(curTick
+ interval
);
66 TsunamiIO::RTCEvent::process()
68 static int intr_count
= 0;
69 DPRINTF(MC146818
, "RTC Timer Interrupt\n");
70 schedule(curTick
+ interval
);
71 //Actually interrupt the processor here
72 tsunami
->cchip
->postRTC();
73 if (intr_count
== 1023)
74 tm
.tm_sec
= (tm
.tm_sec
+ 1) % 60;
76 intr_count
= (intr_count
+ 1) % 1024;
81 TsunamiIO::RTCEvent::description()
83 return "tsunami RTC interrupt";
87 TsunamiIO::RTCEvent::serialize(std::ostream
&os
)
90 SERIALIZE_SCALAR(time
);
94 TsunamiIO::RTCEvent::unserialize(Checkpoint
*cp
, const std::string
§ion
)
97 UNSERIALIZE_SCALAR(time
);
102 // Timer Event for PIT Timers
103 TsunamiIO::ClockEvent::ClockEvent()
104 : Event(&mainEventQueue
)
106 /* This is the PIT Tick Rate. A constant for the 8254 timer. The
107 * Tsunami platform has one of these cycle counters on the Cypress
108 * South Bridge and it is used by linux for estimating the cycle
109 * frequency of the machine it is running on. --Ali
111 interval
= (Tick
)(Clock::Float::s
/ 1193180.0);
113 DPRINTF(Tsunami
, "Clock Event Initilizing\n");
116 current_count
.whole
= 0;
117 latched_count
.whole
= 0;
123 TsunamiIO::ClockEvent::process()
125 DPRINTF(Tsunami
, "Timer Interrupt\n");
127 status
= 0x20; // set bit that linux is looking for
129 schedule(curTick
+ interval
);
131 current_count
.whole
--; //decrement count
135 TsunamiIO::ClockEvent::Program(int count
)
137 DPRINTF(Tsunami
, "Timer set to curTick + %d\n", count
* interval
);
138 schedule(curTick
+ count
* interval
);
141 current_count
.whole
= count
;
145 TsunamiIO::ClockEvent::description()
147 return "tsunami 8254 Interval timer";
151 TsunamiIO::ClockEvent::ChangeMode(uint8_t md
)
157 TsunamiIO::ClockEvent::Status()
163 TsunamiIO::ClockEvent::LatchCount()
168 latched_count
.whole
= current_count
.whole
;
173 TsunamiIO::ClockEvent::Read()
178 return latched_count
.half
.lsb
;
181 return latched_count
.half
.msb
;
186 return current_count
.half
.lsb
;
188 return current_count
.half
.msb
;
195 TsunamiIO::ClockEvent::serialize(std::ostream
&os
)
197 Tick time
= scheduled() ? when() : 0;
198 SERIALIZE_SCALAR(time
);
199 SERIALIZE_SCALAR(status
);
200 SERIALIZE_SCALAR(mode
);
201 SERIALIZE_SCALAR(interval
);
205 TsunamiIO::ClockEvent::unserialize(Checkpoint
*cp
, const std::string
§ion
)
208 UNSERIALIZE_SCALAR(time
);
209 UNSERIALIZE_SCALAR(status
);
210 UNSERIALIZE_SCALAR(mode
);
211 UNSERIALIZE_SCALAR(interval
);
216 TsunamiIO::TsunamiIO(const string
&name
, Tsunami
*t
, time_t init_time
,
217 Addr a
, MemoryController
*mmu
, HierParams
*hier
, Bus
*bus
,
218 Tick pio_latency
, Tick ci
)
219 : PioDevice(name
, t
), addr(a
), clockInterval(ci
), tsunami(t
), rtc(t
, ci
)
221 mmu
->add_child(this, RangeSize(addr
, size
));
224 pioInterface
= newPioInterface(name
, hier
, bus
, this,
225 &TsunamiIO::cacheAccess
);
226 pioInterface
->addAddrRange(RangeSize(addr
, size
));
227 pioLatency
= pio_latency
* bus
->clockRate
;
230 // set the back pointer from tsunami to myself
234 set_time(init_time
== 0 ? time(NULL
) : init_time
);
237 picInterrupting
= false;
241 TsunamiIO::frequency() const
243 return Clock::Frequency
/ clockInterval
;
247 TsunamiIO::set_time(time_t t
)
250 DPRINTFN("Real-time clock set to %s", asctime(&tm
));
254 TsunamiIO::read(MemReqPtr
&req
, uint8_t *data
)
256 DPRINTF(Tsunami
, "io read va=%#x size=%d IOPorrt=%#x\n",
257 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff);
259 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
)) + 0x20;
263 case sizeof(uint8_t):
266 case TSDEV_PIC1_MASK
:
267 *(uint8_t*)data
= ~mask1
;
269 case TSDEV_PIC2_MASK
:
270 *(uint8_t*)data
= ~mask2
;
273 // !!! If this is modified 64bit case needs to be too
274 // Pal code has to do a 64 bit physical read because there is
275 // no load physical byte instruction
276 *(uint8_t*)data
= picr
;
279 // PIC2 not implemnted... just return 0
280 *(uint8_t*)data
= 0x00;
283 *(uint8_t*)data
= timer2
.Status();
285 case TSDEV_TMR0_DATA
:
286 *(uint8_t *)data
= timer0
.Read();
291 *(uint8_t*)data
= uip
<< 7 | 0x26;
295 // DM and 24/12 and UIE
296 *(uint8_t*)data
= 0x46;
299 // If we want to support RTC user access in linux
300 // This won't work, but for now it's fine
301 *(uint8_t*)data
= 0x00;
304 panic("RTC Control Register D not implemented");
306 *(uint8_t *)data
= tm
.tm_sec
;
309 *(uint8_t *)data
= tm
.tm_min
;
312 *(uint8_t *)data
= tm
.tm_hour
;
315 *(uint8_t *)data
= tm
.tm_wday
;
318 *(uint8_t *)data
= tm
.tm_mday
;
321 *(uint8_t *)data
= tm
.tm_mon
+ 1;
324 *(uint8_t *)data
= tm
.tm_year
- UNIX_YEAR_OFFSET
;
327 panic("Unknown RTC Address\n");
330 /* Added for keyboard reads */
332 *(uint8_t *)data
= 0x00;
334 /* Added for ATA PCI DMA */
336 *(uint8_t *)data
= 0x00;
339 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
341 case sizeof(uint16_t):
342 case sizeof(uint32_t):
343 panic("I/O Read - invalid size - va %#x size %d\n",
344 req
->vaddr
, req
->size
);
346 case sizeof(uint64_t):
349 // !!! If this is modified 8bit case needs to be too
350 // Pal code has to do a 64 bit physical read because there is
351 // no load physical byte instruction
352 *(uint64_t*)data
= (uint64_t)picr
;
355 panic("I/O Read - invalid size - va %#x size %d\n",
356 req
->vaddr
, req
->size
);
360 panic("I/O Read - invalid size - va %#x size %d\n",
361 req
->vaddr
, req
->size
);
363 panic("I/O Read - va%#x size %d\n", req
->vaddr
, req
->size
);
369 TsunamiIO::write(MemReqPtr
&req
, const uint8_t *data
)
373 uint8_t dt
= *(uint8_t*)data
;
377 DPRINTF(Tsunami
, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
378 req
->vaddr
, req
->size
, req
->vaddr
& 0xfff, dt64
);
380 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
)) + 0x20;
383 case sizeof(uint8_t):
385 case TSDEV_PIC1_MASK
:
386 mask1
= ~(*(uint8_t*)data
);
387 if ((picr
& mask1
) && !picInterrupting
) {
388 picInterrupting
= true;
389 tsunami
->cchip
->postDRIR(55);
390 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
392 if ((!(picr
& mask1
)) && picInterrupting
) {
393 picInterrupting
= false;
394 tsunami
->cchip
->clearDRIR(55);
395 DPRINTF(Tsunami
, "clearing pic interrupt\n");
398 case TSDEV_PIC2_MASK
:
399 mask2
= *(uint8_t*)data
;
400 //PIC2 Not implemented to interrupt
403 // clear the interrupt on the PIC
404 picr
&= ~(1 << (*(uint8_t*)data
& 0xF));
406 tsunami
->cchip
->clearDRIR(55);
410 case TSDEV_DMA1_RESET
:
412 case TSDEV_DMA2_RESET
:
414 case TSDEV_DMA1_MODE
:
415 mode1
= *(uint8_t*)data
;
417 case TSDEV_DMA2_MODE
:
418 mode2
= *(uint8_t*)data
;
420 case TSDEV_DMA1_MASK
:
421 case TSDEV_DMA2_MASK
:
426 switch((*(uint8_t*)data
>> 4) & 0x3) {
428 switch(*(uint8_t*)data
>> 6) {
436 panic("Read Back Command not implemented\n");
442 panic("Only L/M write and Counter-Latch read supported\n");
445 switch(*(uint8_t*)data
>> 6) {
447 timer0
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
450 timer2
.ChangeMode((*(uint8_t*)data
& 0xF) >> 1);
453 panic("Read Back Command not implemented\n");
456 case TSDEV_TMR2_DATA
:
457 /* two writes before we actually start the Timer
458 so I set a flag in the timerData */
459 if(timerData
& 0x1000) {
461 timerData
+= *(uint8_t*)data
<< 8;
462 timer2
.Program(timerData
);
464 timerData
= *(uint8_t*)data
;
468 case TSDEV_TMR0_DATA
:
469 /* two writes before we actually start the Timer
470 so I set a flag in the timerData */
471 if(timerData
& 0x1000) {
473 timerData
+= *(uint8_t*)data
<< 8;
474 timer0
.Program(timerData
);
476 timerData
= *(uint8_t*)data
;
481 RTCAddress
= *(uint8_t*)data
;
496 tm
.tm_sec
= *(uint8_t *)data
;
499 tm
.tm_min
= *(uint8_t *)data
;
502 tm
.tm_hour
= *(uint8_t *)data
;
505 tm
.tm_wday
= *(uint8_t *)data
;
508 tm
.tm_mday
= *(uint8_t *)data
;
511 tm
.tm_mon
= *(uint8_t *)data
- 1;
514 tm
.tm_year
= *(uint8_t *)data
+ UNIX_YEAR_OFFSET
;
516 //panic("RTC Write not implmented (rtc.o won't work)\n");
519 panic("I/O Write - va%#x size %d\n", req
->vaddr
, req
->size
);
521 case sizeof(uint16_t):
522 case sizeof(uint32_t):
523 case sizeof(uint64_t):
525 panic("I/O Write - invalid size - va %#x size %d\n",
526 req
->vaddr
, req
->size
);
534 TsunamiIO::postPIC(uint8_t bitvector
)
536 //PIC2 Is not implemented, because nothing of interest there
539 tsunami
->cchip
->postDRIR(55);
540 DPRINTF(Tsunami
, "posting pic interrupt to cchip\n");
545 TsunamiIO::clearPIC(uint8_t bitvector
)
547 //PIC2 Is not implemented, because nothing of interest there
549 if (!(picr
& mask1
)) {
550 tsunami
->cchip
->clearDRIR(55);
551 DPRINTF(Tsunami
, "clearing pic interrupt to cchip\n");
556 TsunamiIO::cacheAccess(MemReqPtr
&req
)
558 return curTick
+ pioLatency
;
562 TsunamiIO::serialize(std::ostream
&os
)
564 SERIALIZE_SCALAR(timerData
);
565 SERIALIZE_SCALAR(uip
);
566 SERIALIZE_SCALAR(mask1
);
567 SERIALIZE_SCALAR(mask2
);
568 SERIALIZE_SCALAR(mode1
);
569 SERIALIZE_SCALAR(mode2
);
570 SERIALIZE_SCALAR(picr
);
571 SERIALIZE_SCALAR(picInterrupting
);
572 SERIALIZE_SCALAR(RTCAddress
);
574 // Serialize the timers
575 nameOut(os
, csprintf("%s.timer0", name()));
576 timer0
.serialize(os
);
577 nameOut(os
, csprintf("%s.timer2", name()));
578 timer2
.serialize(os
);
579 nameOut(os
, csprintf("%s.rtc", name()));
584 TsunamiIO::unserialize(Checkpoint
*cp
, const std::string
§ion
)
586 UNSERIALIZE_SCALAR(timerData
);
587 UNSERIALIZE_SCALAR(uip
);
588 UNSERIALIZE_SCALAR(mask1
);
589 UNSERIALIZE_SCALAR(mask2
);
590 UNSERIALIZE_SCALAR(mode1
);
591 UNSERIALIZE_SCALAR(mode2
);
592 UNSERIALIZE_SCALAR(picr
);
593 UNSERIALIZE_SCALAR(picInterrupting
);
594 UNSERIALIZE_SCALAR(RTCAddress
);
596 // Unserialize the timers
597 timer0
.unserialize(cp
, csprintf("%s.timer0", section
));
598 timer2
.unserialize(cp
, csprintf("%s.timer2", section
));
599 rtc
.unserialize(cp
, csprintf("%s.rtc", section
));
602 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
604 SimObjectParam
<Tsunami
*> tsunami
;
606 SimObjectParam
<MemoryController
*> mmu
;
608 SimObjectParam
<Bus
*> io_bus
;
609 Param
<Tick
> pio_latency
;
610 SimObjectParam
<HierParams
*> hier
;
611 Param
<Tick
> frequency
;
613 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO
)
615 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
617 INIT_PARAM(tsunami
, "Tsunami"),
618 INIT_PARAM(time
, "System time to use (0 for actual time"),
619 INIT_PARAM(mmu
, "Memory Controller"),
620 INIT_PARAM(addr
, "Device Address"),
621 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
622 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
623 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
),
624 INIT_PARAM(frequency
, "clock interrupt frequency")
626 END_INIT_SIM_OBJECT_PARAMS(TsunamiIO
)
628 CREATE_SIM_OBJECT(TsunamiIO
)
630 return new TsunamiIO(getInstanceName(), tsunami
, time
, addr
, mmu
, hier
,
631 io_bus
, pio_latency
, frequency
);
634 REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO
)