2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Tsunami I/O Space mapping including RTC/timer interrupts
33 #ifndef __DEV_TSUNAMI_IO_HH__
34 #define __DEV_TSUNAMI_IO_HH__
36 #include "dev/io_device.hh"
37 #include "base/range.hh"
38 #include "dev/tsunami.hh"
39 #include "sim/eventq.hh"
41 class MemoryController;
44 * Tsunami I/O device is a catch all for all the south bridge stuff we care
47 class TsunamiIO : public PioDevice
50 /** The base address of this device */
53 /** The size of mappad from the above address */
54 static const Addr size = 0xff;
59 /** Real-Time Clock (MC146818) */
63 /** Event for RTC periodic interrupt */
64 struct RTCEvent : public Event
66 /** A pointer back to tsunami to create interrupt the processor. */
70 RTCEvent(Tsunami* t, Tick i);
72 /** Schedule the RTC periodic interrupt */
75 /** Event process to occur at interrupt*/
76 virtual void process();
78 /** Event description */
79 virtual const char *description();
84 const std::string &name() const { return _name; }
86 /** RTC periodic interrupt event */
89 /** Current RTC register address/index */
92 /** Data for real-time clock function */
94 uint8_t clock_data[10];
110 /** RTC status register A */
113 /** RTC status register B */
117 RTC(const std::string &name, Tsunami* t, Tick i);
119 /** Set the initial RTC time/date */
120 void set_time(time_t t);
122 /** RTC address port: write address of RTC RAM data to access */
123 void writeAddr(const uint8_t *data);
125 /** RTC write data */
126 void writeData(const uint8_t *data);
129 void readData(uint8_t *data);
132 * Serialize this object to the given output stream.
133 * @param os The stream to serialize to.
135 void serialize(const std::string &base, std::ostream &os);
138 * Reconstruct the state of this object from a checkpoint.
139 * @param cp The checkpoint use.
140 * @param section The section name of this object
142 void unserialize(const std::string &base, Checkpoint *cp,
143 const std::string §ion);
146 /** Programmable Interval Timer (Intel 8254) */
149 /** Counter element for PIT */
152 /** Event for counter interrupt */
153 class CounterEvent : public Event
156 /** Pointer back to Counter */
161 CounterEvent(Counter*);
164 virtual void process();
166 /** Event description */
167 virtual const char *description();
169 friend class Counter;
174 const std::string &name() const { return _name; }
178 /** Current count value */
182 uint16_t latched_count;
184 /** Interrupt period */
187 /** Current mode of operation */
190 /** Output goes high when the counter reaches zero */
193 /** State of the count latch */
196 /** Set of values for read_byte and write_byte */
199 /** Determine which byte of a 16-bit count value to read/write */
200 uint8_t read_byte, write_byte;
203 Counter(const std::string &name);
205 /** Latch the current count (if one is not already latched) */
208 /** Set the read/write mode */
209 void setRW(int rw_val);
211 /** Set operational mode */
212 void setMode(int mode_val);
214 /** Set count encoding */
215 void setBCD(int bcd_val);
217 /** Read a count byte */
218 void read(uint8_t *data);
220 /** Write a count byte */
221 void write(const uint8_t *data);
223 /** Is the output high? */
227 * Serialize this object to the given output stream.
228 * @param os The stream to serialize to.
230 void serialize(const std::string &base, std::ostream &os);
233 * Reconstruct the state of this object from a checkpoint.
234 * @param cp The checkpoint use.
235 * @param section The section name of this object
237 void unserialize(const std::string &base, Checkpoint *cp,
238 const std::string §ion);
243 const std::string &name() const { return _name; }
245 /** PIT has three seperate counters */
249 /** Public way to access individual counters (avoid array accesses) */
254 PITimer(const std::string &name);
256 /** Write control word */
257 void writeControl(const uint8_t* data);
260 * Serialize this object to the given output stream.
261 * @param os The stream to serialize to.
263 void serialize(const std::string &base, std::ostream &os);
266 * Reconstruct the state of this object from a checkpoint.
267 * @param cp The checkpoint use.
268 * @param section The section name of this object
270 void unserialize(const std::string &base, Checkpoint *cp,
271 const std::string §ion);
274 /** Mask of the PIC1 */
277 /** Mask of the PIC2 */
280 /** Mode of PIC1. Not used for anything */
283 /** Mode of PIC2. Not used for anything */
286 /** Raw PIC interrupt register before masking */
287 uint8_t picr; //Raw PIC interrput register
289 /** Is the pic interrupting right now or not. */
290 bool picInterrupting;
294 /** A pointer to the Tsunami device which be belong to */
297 /** Intel 8253 Periodic Interval Timer */
302 /** The interval is set via two writes to the PIT.
303 * This variable contains a flag as to how many writes have happened, and
310 * Return the freqency of the RTC
311 * @return interrupt rate of the RTC
313 Tick frequency() const;
316 * Initialize all the data for devices supported by Tsunami I/O.
317 * @param name name of this device.
318 * @param t pointer back to the Tsunami object that we belong to.
319 * @param init_time Time (as in seconds since 1970) to set RTC to.
320 * @param a address we are mapped at.
321 * @param mmu pointer to the memory controller that sends us events.
323 TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
324 Addr a, MemoryController *mmu, HierParams *hier, Bus *pio_bus,
325 Tick pio_latency, Tick ci);
328 * Process a read to one of the devices we are emulating.
329 * @param req Contains the address to read from.
330 * @param data A pointer to write the read data to.
331 * @return The fault condition of the access.
333 virtual Fault * read(MemReqPtr &req, uint8_t *data);
336 * Process a write to one of the devices we emulate.
337 * @param req Contains the address to write to.
338 * @param data The data to write.
339 * @return The fault condition of the access.
341 virtual Fault * write(MemReqPtr &req, const uint8_t *data);
344 * Post an PIC interrupt to the CPU via the CChip
345 * @param bitvector interrupt to post.
347 void postPIC(uint8_t bitvector);
350 * Clear a posted interrupt
351 * @param bitvector interrupt to clear
353 void clearPIC(uint8_t bitvector);
356 * Serialize this object to the given output stream.
357 * @param os The stream to serialize to.
359 virtual void serialize(std::ostream &os);
362 * Reconstruct the state of this object from a checkpoint.
363 * @param cp The checkpoint use.
364 * @param section The section name of this object
366 virtual void unserialize(Checkpoint *cp, const std::string §ion);
368 Tick cacheAccess(MemReqPtr &req);
371 #endif // __DEV_TSUNAMI_IO_HH__