2 * Copyright (c) 2004 The Regents of The University of Michigan
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30 * Tsunami Fake I/O Space mapping including RTC/timer interrupts
33 #ifndef __TSUNAMI_DMA_HH__
34 #define __TSUNAMI_DMA_HH__
36 #include "mem/functional_mem/functional_memory.hh"
37 #include "dev/tsunami.hh"
39 /** How often the RTC interrupts */
40 static const int RTC_RATE = 1024;
43 * Tsunami I/O device is a catch all for all the south bridge stuff we care
46 class TsunamiIO : public FunctionalMemory
49 /** The base address of this device */
52 /** The size of mappad from the above address */
53 static const Addr size = 0xff;
57 /** In Tsunami RTC only has two i/o ports one for data and one for address,
58 * so you write the address and then read/write the data. This store the
59 * address you are going to be reading from on a read.
66 * The ClockEvent is handles the PIT interrupts
68 class ClockEvent : public Event
71 /** how often the PIT fires */
73 /** The mode of the PIT */
75 /** The status of the PIT */
80 * Just set the mode to 0
85 * processs the timer event
87 virtual void process();
90 * Returns a description of this event
91 * @return the description
93 virtual const char *description();
96 * Schedule a timer interrupt to occur sometime in the future.
98 void Program(int count);
101 * Write the mode bits of the PIT.
102 * @param mode the new mode
104 void ChangeMode(uint8_t mode);
107 * The current PIT status.
108 * @return the status of the PIT
115 * Process RTC timer events and generate interrupts appropriately.
117 class RTCEvent : public Event
120 /** A pointer back to tsunami to create interrupt the processor. */
123 /** RTC Event initializes the RTC event by scheduling an event
124 * RTC_RATE times pre second. */
125 RTCEvent(Tsunami* t);
128 * Interrupth the processor and reschedule the event.
130 virtual void process();
133 * Return a description of this event.
134 * @return a description
136 virtual const char *description();
139 /** uip UpdateInProgess says that the rtc is updating, but we just fake it
140 * by alternating it on every read of the bit since we are going to
141 * override the loop_per_jiffy time that it is trying to use the UIP to
146 /** Mask of the PIC1 */
149 /** Mask of the PIC2 */
152 /** Mode of PIC1. Not used for anything */
155 /** Mode of PIC2. Not used for anything */
158 /** Raw PIC interrupt register before masking */
159 uint8_t picr; //Raw PIC interrput register
161 /** Is the pic interrupting right now or not. */
162 bool picInterrupting;
164 /** A pointer to the Tsunami device which be belong to */
168 * This timer is initilized, but after I wrote the code
169 * it doesn't seem to be used again, and best I can tell
170 * it too is not connected to any interrupt port
175 * This timer is used to control the speaker, which
176 * we normally could care less about, however it is
177 * also used to calculated the clockspeed and hense
178 * bogomips which is kinda important to the scheduler
179 * so we need to implemnt it although after boot I can't
180 * imagine we would be playing with the PC speaker much
184 /** This is the event used to interrupt the cpu like an RTC. */
187 /** The interval is set via two writes to the PIT.
188 * This variable contains a flag as to how many writes have happened, and
196 * Return the freqency of the RTC
197 * @return interrupt rate of the RTC
199 Tick frequency() const { return RTC_RATE; }
203 * Initialize all the data for devices supported by Tsunami I/O.
204 * @param name name of this device.
205 * @param t pointer back to the Tsunami object that we belong to.
206 * @param init_time Time (as in seconds since 1970) to set RTC to.
207 * @param a address we are mapped at.
208 * @param mmu pointer to the memory controller that sends us events.
210 TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
211 Addr a, MemoryController *mmu);
214 * Create the tm struct from seconds since 1970
216 void set_time(time_t t);
219 * Process a read to one of the devices we are emulating.
220 * @param req Contains the address to read from.
221 * @param data A pointer to write the read data to.
222 * @return The fault condition of the access.
224 virtual Fault read(MemReqPtr &req, uint8_t *data);
227 * Process a write to one of the devices we emulate.
228 * @param req Contains the address to write to.
229 * @param data The data to write.
230 * @return The fault condition of the access.
232 virtual Fault write(MemReqPtr &req, const uint8_t *data);
235 * Post an PIC interrupt to the CPU via the CChip
236 * @param bitvector interrupt to post.
238 void postPIC(uint8_t bitvector);
241 * Clear a posted interrupt
242 * @param bitvector interrupt to clear
244 void clearPIC(uint8_t bitvector);
247 * Serialize this object to the given output stream.
248 * @param os The stream to serialize to.
250 virtual void serialize(std::ostream &os);
254 * Reconstruct the state of this object from a checkpoint.
255 * @param cp The checkpoint use.
256 * @param section The section name of this object
258 virtual void unserialize(Checkpoint *cp, const std::string §ion);
261 #endif // __TSUNAMI_IO_HH__