11 #include "base/trace.hh"
12 #include "cpu/exec_context.hh"
13 #include "dev/console.hh"
14 #include "dev/etherdev.hh"
15 #include "dev/scsi_ctrl.hh"
16 #include "dev/tlaser_clock.hh"
17 #include "dev/tsunami_pchip.hh"
18 #include "dev/tsunamireg.h"
19 #include "dev/tsunami.hh"
20 #include "mem/functional_mem/memory_control.hh"
21 #include "mem/functional_mem/physical_memory.hh"
22 #include "sim/builder.hh"
23 #include "sim/system.hh"
27 TsunamiPChip::TsunamiPChip(const string
&name
, Tsunami
*t
, Addr a
,
28 MemoryController
*mmu
)
29 : FunctionalMemory(name
), addr(a
), tsunami(t
)
31 mmu
->add_child(this, Range
<Addr
>(addr
, addr
+ size
));
33 for (int i
= 0; i
< 4; i
++) {
39 //Set back pointer in tsunami
40 tsunami
->pchip
= this;
44 TsunamiPChip::read(MemReqPtr
&req
, uint8_t *data
)
46 DPRINTF(Tsunami
, "read va=%#x size=%d\n",
47 req
->vaddr
, req
->size
);
49 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
)) >> 6;
53 case sizeof(uint64_t):
56 *(uint64_t*)data
= wsba
[0];
59 *(uint64_t*)data
= wsba
[1];
62 *(uint64_t*)data
= wsba
[2];
65 *(uint64_t*)data
= wsba
[3];
68 *(uint64_t*)data
= wsm
[0];
71 *(uint64_t*)data
= wsm
[1];
74 *(uint64_t*)data
= wsm
[2];
77 *(uint64_t*)data
= wsm
[3];
80 *(uint64_t*)data
= tba
[0];
83 *(uint64_t*)data
= tba
[1];
86 *(uint64_t*)data
= tba
[2];
89 *(uint64_t*)data
= tba
[3];
92 // might want to change the clock??
93 *(uint64_t*)data
= 0x00; // try this
96 panic("PC_PLAT not implemented\n");
98 panic("PC_RES not implemented\n");
100 panic("PC_PERROR not implemented\n");
101 case TSDEV_PC_PERRMASK
:
102 panic("PC_PERRMASK not implemented\n");
103 case TSDEV_PC_PERRSET
:
104 panic("PC_PERRSET not implemented\n");
106 panic("PC_TLBIV not implemented\n");
108 *(uint64_t*)data
= 0x00; // shouldn't be readable, but linux
110 case TSDEV_PC_PMONCTL
:
111 panic("PC_PMONCTL not implemented\n");
112 case TSDEV_PC_PMONCNT
:
113 panic("PC_PMONCTN not implemented\n");
115 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
120 case sizeof(uint32_t):
121 case sizeof(uint16_t):
122 case sizeof(uint8_t):
124 panic("invalid access size(?) for tsunami register!\n\n");
126 DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr
, req
->size
);
132 TsunamiPChip::write(MemReqPtr
&req
, const uint8_t *data
)
134 DPRINTF(Tsunami
, "write - va=%#x size=%d \n",
135 req
->vaddr
, req
->size
);
137 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
)) >> 6;
141 case sizeof(uint64_t):
144 wsba
[0] = *(uint64_t*)data
;
147 wsba
[1] = *(uint64_t*)data
;
150 wsba
[2] = *(uint64_t*)data
;
153 wsba
[3] = *(uint64_t*)data
;
156 wsm
[0] = *(uint64_t*)data
;
159 wsm
[1] = *(uint64_t*)data
;
162 wsm
[2] = *(uint64_t*)data
;
165 wsm
[3] = *(uint64_t*)data
;
168 tba
[0] = *(uint64_t*)data
;
171 tba
[1] = *(uint64_t*)data
;
174 tba
[2] = *(uint64_t*)data
;
177 tba
[3] = *(uint64_t*)data
;
180 // might want to change the clock??
181 //*(uint64_t*)data; // try this
184 panic("PC_PLAT not implemented\n");
186 panic("PC_RES not implemented\n");
187 case TSDEV_PC_PERROR
:
188 panic("PC_PERROR not implemented\n");
189 case TSDEV_PC_PERRMASK
:
190 panic("PC_PERRMASK not implemented\n");
191 case TSDEV_PC_PERRSET
:
192 panic("PC_PERRSET not implemented\n");
194 panic("PC_TLBIV not implemented\n");
196 return No_Fault
; // value ignored, supposted to invalidate SG TLB
197 case TSDEV_PC_PMONCTL
:
198 panic("PC_PMONCTL not implemented\n");
199 case TSDEV_PC_PMONCNT
:
200 panic("PC_PMONCTN not implemented\n");
202 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
207 case sizeof(uint32_t):
208 case sizeof(uint16_t):
209 case sizeof(uint8_t):
211 panic("invalid access size(?) for tsunami register!\n\n");
214 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr
, req
->size
);
219 #define DMA_ADDR_MASK ULL(0x3ffffffff)
222 TsunamiPChip::translatePciToDma(Addr busAddr
)
224 // compare the address to the window base registers
225 uint64_t tbaMask
= 0;
228 uint64_t windowMask
= 0;
229 uint64_t windowBase
= 0;
231 uint64_t pteEntry
= 0;
236 for (int i
= 0; i
< 4; i
++) {
237 windowBase
= wsba
[i
];
238 windowMask
= ~wsm
[i
] & (0x7ff << 20);
240 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
243 if (wsba
[i
] & 0x1) { // see if enabled
244 if (wsba
[i
] & 0x2) { // see if SG bit is set
246 This currently is faked by just doing a direct
247 read from memory, however, to be realistic, this
248 needs to actually do a bus transaction. The process
249 is explained in the tsunami documentation on page
250 10-12 and basically munges the address to look up a
251 PTE from a table in memory and then uses that mapping
252 to create an address for the SG page
255 tbaMask
= ~(((wsm
[i
] & (0x7ff << 20)) >> 10) | 0x3ff);
256 baMask
= (wsm
[i
] & (0x7ff << 20)) | (0x7f << 13);
257 pteAddr
= (tba
[i
] & tbaMask
) | ((busAddr
& baMask
) >> 10);
259 memcpy((void *)&pteEntry
,
261 physmem
->dma_addr(pteAddr
, sizeof(uint64_t)),
264 dmaAddr
= ((pteEntry
& ~0x1) << 12) | (busAddr
& 0x1fff);
267 baMask
= (wsm
[i
] & (0x7ff << 20)) | 0xfffff;
269 dmaAddr
= (tba
[i
] & tbaMask
) | (busAddr
& baMask
);
272 return (dmaAddr
& DMA_ADDR_MASK
);
281 TsunamiPChip::serialize(std::ostream
&os
)
283 SERIALIZE_ARRAY(wsba
, 4);
284 SERIALIZE_ARRAY(wsm
, 4);
285 SERIALIZE_ARRAY(tba
, 4);
289 TsunamiPChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
291 UNSERIALIZE_ARRAY(wsba
, 4);
292 UNSERIALIZE_ARRAY(wsm
, 4);
293 UNSERIALIZE_ARRAY(tba
, 4);
296 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
298 SimObjectParam
<Tsunami
*> tsunami
;
299 SimObjectParam
<MemoryController
*> mmu
;
302 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
304 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
306 INIT_PARAM(tsunami
, "Tsunami"),
307 INIT_PARAM(mmu
, "Memory Controller"),
308 INIT_PARAM(addr
, "Device Address")
310 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
312 CREATE_SIM_OBJECT(TsunamiPChip
)
314 return new TsunamiPChip(getInstanceName(), tsunami
, addr
, mmu
);
317 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip
)