11 #include "base/trace.hh"
12 #include "cpu/exec_context.hh"
13 #include "dev/console.hh"
14 #include "dev/etherdev.hh"
15 #include "dev/scsi_ctrl.hh"
16 #include "dev/tlaser_clock.hh"
17 #include "dev/tsunami_pchip.hh"
18 #include "dev/tsunamireg.h"
19 #include "dev/tsunami.hh"
20 #include "mem/functional_mem/memory_control.hh"
21 #include "sim/builder.hh"
22 #include "sim/system.hh"
26 TsunamiPChip::TsunamiPChip(const string
&name
, Tsunami
*t
,
27 Addr addr
, Addr mask
, MemoryController
*mmu
)
28 : MmapDevice(name
, addr
, mask
, mmu
), tsunami(t
)
43 //Set back pointer in tsunami
44 tsunami
->pchip
= this;
48 TsunamiPChip::read(MemReqPtr
&req
, uint8_t *data
)
50 DPRINTF(Tsunami
, "read va=%#x size=%d\n",
51 req
->vaddr
, req
->size
);
53 Addr daddr
= (req
->paddr
& addr_mask
) >> 6;
54 // ExecContext *xc = req->xc;
55 // int cpuid = xc->cpu_id;
59 case sizeof(uint64_t):
62 *(uint64_t*)data
= wsba0
;
65 *(uint64_t*)data
= wsba1
;
68 *(uint64_t*)data
= wsba2
;
71 *(uint64_t*)data
= wsba3
;
74 *(uint64_t*)data
= wsm0
;
77 *(uint64_t*)data
= wsm1
;
80 *(uint64_t*)data
= wsm2
;
83 *(uint64_t*)data
= wsm3
;
86 *(uint64_t*)data
= tba0
;
89 *(uint64_t*)data
= tba1
;
92 *(uint64_t*)data
= tba2
;
95 *(uint64_t*)data
= tba3
;
98 // might want to change the clock??
99 *(uint64_t*)data
= 0x00; // try this
102 panic("PC_PLAT not implemented\n");
104 panic("PC_RES not implemented\n");
105 case TSDEV_PC_PERROR
:
106 panic("PC_PERROR not implemented\n");
107 case TSDEV_PC_PERRMASK
:
108 panic("PC_PERRMASK not implemented\n");
109 case TSDEV_PC_PERRSET
:
110 panic("PC_PERRSET not implemented\n");
112 panic("PC_TLBIV not implemented\n");
114 *(uint64_t*)data
= 0x00; // shouldn't be readable, but linux
116 case TSDEV_PC_PMONCTL
:
117 panic("PC_PMONCTL not implemented\n");
118 case TSDEV_PC_PMONCNT
:
119 panic("PC_PMONCTN not implemented\n");
121 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
126 case sizeof(uint32_t):
127 case sizeof(uint16_t):
128 case sizeof(uint8_t):
130 panic("invalid access size(?) for tsunami register!\n\n");
132 DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr
, req
->size
);
138 TsunamiPChip::write(MemReqPtr
&req
, const uint8_t *data
)
140 DPRINTF(Tsunami
, "write - va=%#x size=%d \n",
141 req
->vaddr
, req
->size
);
143 Addr daddr
= (req
->paddr
& addr_mask
) >> 6;
147 case sizeof(uint64_t):
150 wsba0
= *(uint64_t*)data
;
153 wsba1
= *(uint64_t*)data
;
156 wsba2
= *(uint64_t*)data
;
159 wsba3
= *(uint64_t*)data
;
162 wsm0
= *(uint64_t*)data
;
165 wsm1
= *(uint64_t*)data
;
168 wsm2
= *(uint64_t*)data
;
171 wsm3
= *(uint64_t*)data
;
174 tba0
= *(uint64_t*)data
;
177 tba1
= *(uint64_t*)data
;
180 tba2
= *(uint64_t*)data
;
183 tba3
= *(uint64_t*)data
;
186 // might want to change the clock??
187 //*(uint64_t*)data; // try this
190 panic("PC_PLAT not implemented\n");
192 panic("PC_RES not implemented\n");
193 case TSDEV_PC_PERROR
:
194 panic("PC_PERROR not implemented\n");
195 case TSDEV_PC_PERRMASK
:
196 panic("PC_PERRMASK not implemented\n");
197 case TSDEV_PC_PERRSET
:
198 panic("PC_PERRSET not implemented\n");
200 panic("PC_TLBIV not implemented\n");
202 return No_Fault
; // value ignored, supposted to invalidate SG TLB
203 case TSDEV_PC_PMONCTL
:
204 panic("PC_PMONCTL not implemented\n");
205 case TSDEV_PC_PMONCNT
:
206 panic("PC_PMONCTN not implemented\n");
208 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
213 case sizeof(uint32_t):
214 case sizeof(uint16_t):
215 case sizeof(uint8_t):
217 panic("invalid access size(?) for tsunami register!\n\n");
220 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr
, req
->size
);
226 TsunamiPChip::serialize(std::ostream
&os
)
228 // code should be written
232 TsunamiPChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
234 //code should be written
237 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
239 SimObjectParam
<Tsunami
*> tsunami
;
240 SimObjectParam
<MemoryController
*> mmu
;
244 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
246 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
248 INIT_PARAM(tsunami
, "Tsunami"),
249 INIT_PARAM(mmu
, "Memory Controller"),
250 INIT_PARAM(addr
, "Device Address"),
251 INIT_PARAM(mask
, "Address Mask")
253 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
255 CREATE_SIM_OBJECT(TsunamiPChip
)
257 return new TsunamiPChip(getInstanceName(), tsunami
, addr
, mask
, mmu
);
260 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip
)