11 #include "base/trace.hh"
12 #include "cpu/exec_context.hh"
13 #include "dev/console.hh"
14 #include "dev/etherdev.hh"
15 #include "dev/scsi_ctrl.hh"
16 #include "dev/tlaser_clock.hh"
17 #include "dev/tsunami_pchip.hh"
18 #include "dev/tsunamireg.h"
19 #include "dev/tsunami.hh"
20 #include "mem/functional_mem/memory_control.hh"
21 #include "sim/builder.hh"
22 #include "sim/system.hh"
26 TsunamiPChip::TsunamiPChip(const string
&name
, Tsunami
*t
, Addr a
,
27 MemoryController
*mmu
)
28 : FunctionalMemory(name
), addr(a
), tsunami(t
)
30 mmu
->add_child(this, Range
<Addr
>(addr
, addr
+ size
));
45 //Set back pointer in tsunami
46 tsunami
->pchip
= this;
50 TsunamiPChip::read(MemReqPtr
&req
, uint8_t *data
)
52 DPRINTF(Tsunami
, "read va=%#x size=%d\n",
53 req
->vaddr
, req
->size
);
55 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
)) >> 6;
56 // ExecContext *xc = req->xc;
57 // int cpuid = xc->cpu_id;
61 case sizeof(uint64_t):
64 *(uint64_t*)data
= wsba0
;
67 *(uint64_t*)data
= wsba1
;
70 *(uint64_t*)data
= wsba2
;
73 *(uint64_t*)data
= wsba3
;
76 *(uint64_t*)data
= wsm0
;
79 *(uint64_t*)data
= wsm1
;
82 *(uint64_t*)data
= wsm2
;
85 *(uint64_t*)data
= wsm3
;
88 *(uint64_t*)data
= tba0
;
91 *(uint64_t*)data
= tba1
;
94 *(uint64_t*)data
= tba2
;
97 *(uint64_t*)data
= tba3
;
100 // might want to change the clock??
101 *(uint64_t*)data
= 0x00; // try this
104 panic("PC_PLAT not implemented\n");
106 panic("PC_RES not implemented\n");
107 case TSDEV_PC_PERROR
:
108 panic("PC_PERROR not implemented\n");
109 case TSDEV_PC_PERRMASK
:
110 panic("PC_PERRMASK not implemented\n");
111 case TSDEV_PC_PERRSET
:
112 panic("PC_PERRSET not implemented\n");
114 panic("PC_TLBIV not implemented\n");
116 *(uint64_t*)data
= 0x00; // shouldn't be readable, but linux
118 case TSDEV_PC_PMONCTL
:
119 panic("PC_PMONCTL not implemented\n");
120 case TSDEV_PC_PMONCNT
:
121 panic("PC_PMONCTN not implemented\n");
123 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
128 case sizeof(uint32_t):
129 case sizeof(uint16_t):
130 case sizeof(uint8_t):
132 panic("invalid access size(?) for tsunami register!\n\n");
134 DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr
, req
->size
);
140 TsunamiPChip::write(MemReqPtr
&req
, const uint8_t *data
)
142 DPRINTF(Tsunami
, "write - va=%#x size=%d \n",
143 req
->vaddr
, req
->size
);
145 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
)) >> 6;
149 case sizeof(uint64_t):
152 wsba0
= *(uint64_t*)data
;
155 wsba1
= *(uint64_t*)data
;
158 wsba2
= *(uint64_t*)data
;
161 wsba3
= *(uint64_t*)data
;
164 wsm0
= *(uint64_t*)data
;
167 wsm1
= *(uint64_t*)data
;
170 wsm2
= *(uint64_t*)data
;
173 wsm3
= *(uint64_t*)data
;
176 tba0
= *(uint64_t*)data
;
179 tba1
= *(uint64_t*)data
;
182 tba2
= *(uint64_t*)data
;
185 tba3
= *(uint64_t*)data
;
188 // might want to change the clock??
189 //*(uint64_t*)data; // try this
192 panic("PC_PLAT not implemented\n");
194 panic("PC_RES not implemented\n");
195 case TSDEV_PC_PERROR
:
196 panic("PC_PERROR not implemented\n");
197 case TSDEV_PC_PERRMASK
:
198 panic("PC_PERRMASK not implemented\n");
199 case TSDEV_PC_PERRSET
:
200 panic("PC_PERRSET not implemented\n");
202 panic("PC_TLBIV not implemented\n");
204 return No_Fault
; // value ignored, supposted to invalidate SG TLB
205 case TSDEV_PC_PMONCTL
:
206 panic("PC_PMONCTL not implemented\n");
207 case TSDEV_PC_PMONCNT
:
208 panic("PC_PMONCTN not implemented\n");
210 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
215 case sizeof(uint32_t):
216 case sizeof(uint16_t):
217 case sizeof(uint8_t):
219 panic("invalid access size(?) for tsunami register!\n\n");
222 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr
, req
->size
);
228 TsunamiPChip::serialize(std::ostream
&os
)
230 SERIALIZE_SCALAR(wsba0
);
231 SERIALIZE_SCALAR(wsba1
);
232 SERIALIZE_SCALAR(wsba2
);
233 SERIALIZE_SCALAR(wsba3
);
234 SERIALIZE_SCALAR(wsm0
);
235 SERIALIZE_SCALAR(wsm1
);
236 SERIALIZE_SCALAR(wsm2
);
237 SERIALIZE_SCALAR(wsm3
);
238 SERIALIZE_SCALAR(tba0
);
239 SERIALIZE_SCALAR(tba1
);
240 SERIALIZE_SCALAR(tba2
);
241 SERIALIZE_SCALAR(tba3
);
246 TsunamiPChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
248 UNSERIALIZE_SCALAR(wsba0
);
249 UNSERIALIZE_SCALAR(wsba1
);
250 UNSERIALIZE_SCALAR(wsba2
);
251 UNSERIALIZE_SCALAR(wsba3
);
252 UNSERIALIZE_SCALAR(wsm0
);
253 UNSERIALIZE_SCALAR(wsm1
);
254 UNSERIALIZE_SCALAR(wsm2
);
255 UNSERIALIZE_SCALAR(wsm3
);
256 UNSERIALIZE_SCALAR(tba0
);
257 UNSERIALIZE_SCALAR(tba1
);
258 UNSERIALIZE_SCALAR(tba2
);
259 UNSERIALIZE_SCALAR(tba3
);
263 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
265 SimObjectParam
<Tsunami
*> tsunami
;
266 SimObjectParam
<MemoryController
*> mmu
;
269 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
271 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
273 INIT_PARAM(tsunami
, "Tsunami"),
274 INIT_PARAM(mmu
, "Memory Controller"),
275 INIT_PARAM(addr
, "Device Address")
277 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
279 CREATE_SIM_OBJECT(TsunamiPChip
)
281 return new TsunamiPChip(getInstanceName(), tsunami
, addr
, mmu
);
284 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip
)