2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include "base/trace.hh"
38 #include "dev/tsunami_pchip.hh"
39 #include "dev/tsunamireg.h"
40 #include "dev/tsunami.hh"
41 #include "mem/bus/bus.hh"
42 #include "mem/bus/pio_interface.hh"
43 #include "mem/bus/pio_interface_impl.hh"
44 #include "mem/functional_mem/memory_control.hh"
45 #include "mem/functional_mem/physical_memory.hh"
46 #include "sim/builder.hh"
47 #include "sim/system.hh"
51 TsunamiPChip::TsunamiPChip(const string
&name
, Tsunami
*t
, Addr a
,
52 MemoryController
*mmu
, HierParams
*hier
,
54 : PioDevice(name
), addr(a
), tsunami(t
)
56 mmu
->add_child(this, Range
<Addr
>(addr
, addr
+ size
));
58 for (int i
= 0; i
< 4; i
++) {
65 pioInterface
= newPioInterface(name
, hier
, bus
, this,
66 &TsunamiPChip::cacheAccess
);
67 pioInterface
->addAddrRange(addr
, addr
+ size
- 1);
71 // initialize pchip control register
72 pctl
= (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
74 //Set back pointer in tsunami
75 tsunami
->pchip
= this;
79 TsunamiPChip::read(MemReqPtr
&req
, uint8_t *data
)
81 DPRINTF(Tsunami
, "read va=%#x size=%d\n",
82 req
->vaddr
, req
->size
);
84 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
)) >> 6;
88 case sizeof(uint64_t):
91 *(uint64_t*)data
= wsba
[0];
94 *(uint64_t*)data
= wsba
[1];
97 *(uint64_t*)data
= wsba
[2];
100 *(uint64_t*)data
= wsba
[3];
103 *(uint64_t*)data
= wsm
[0];
106 *(uint64_t*)data
= wsm
[1];
109 *(uint64_t*)data
= wsm
[2];
112 *(uint64_t*)data
= wsm
[3];
115 *(uint64_t*)data
= tba
[0];
118 *(uint64_t*)data
= tba
[1];
121 *(uint64_t*)data
= tba
[2];
124 *(uint64_t*)data
= tba
[3];
127 *(uint64_t*)data
= pctl
;
130 panic("PC_PLAT not implemented\n");
132 panic("PC_RES not implemented\n");
133 case TSDEV_PC_PERROR
:
134 *(uint64_t*)data
= 0x00;
136 case TSDEV_PC_PERRMASK
:
137 *(uint64_t*)data
= 0x00;
139 case TSDEV_PC_PERRSET
:
140 panic("PC_PERRSET not implemented\n");
142 panic("PC_TLBIV not implemented\n");
144 *(uint64_t*)data
= 0x00; // shouldn't be readable, but linux
146 case TSDEV_PC_PMONCTL
:
147 panic("PC_PMONCTL not implemented\n");
148 case TSDEV_PC_PMONCNT
:
149 panic("PC_PMONCTN not implemented\n");
151 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
156 case sizeof(uint32_t):
157 case sizeof(uint16_t):
158 case sizeof(uint8_t):
160 panic("invalid access size(?) for tsunami register!\n\n");
162 DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr
, req
->size
);
168 TsunamiPChip::write(MemReqPtr
&req
, const uint8_t *data
)
170 DPRINTF(Tsunami
, "write - va=%#x size=%d \n",
171 req
->vaddr
, req
->size
);
173 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
)) >> 6;
177 case sizeof(uint64_t):
180 wsba
[0] = *(uint64_t*)data
;
183 wsba
[1] = *(uint64_t*)data
;
186 wsba
[2] = *(uint64_t*)data
;
189 wsba
[3] = *(uint64_t*)data
;
192 wsm
[0] = *(uint64_t*)data
;
195 wsm
[1] = *(uint64_t*)data
;
198 wsm
[2] = *(uint64_t*)data
;
201 wsm
[3] = *(uint64_t*)data
;
204 tba
[0] = *(uint64_t*)data
;
207 tba
[1] = *(uint64_t*)data
;
210 tba
[2] = *(uint64_t*)data
;
213 tba
[3] = *(uint64_t*)data
;
216 pctl
= *(uint64_t*)data
;
219 panic("PC_PLAT not implemented\n");
221 panic("PC_RES not implemented\n");
222 case TSDEV_PC_PERROR
:
224 case TSDEV_PC_PERRMASK
:
225 panic("PC_PERRMASK not implemented\n");
226 case TSDEV_PC_PERRSET
:
227 panic("PC_PERRSET not implemented\n");
229 panic("PC_TLBIV not implemented\n");
231 return No_Fault
; // value ignored, supposted to invalidate SG TLB
232 case TSDEV_PC_PMONCTL
:
233 panic("PC_PMONCTL not implemented\n");
234 case TSDEV_PC_PMONCNT
:
235 panic("PC_PMONCTN not implemented\n");
237 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
242 case sizeof(uint32_t):
243 case sizeof(uint16_t):
244 case sizeof(uint8_t):
246 panic("invalid access size(?) for tsunami register!\n\n");
249 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr
, req
->size
);
254 #define DMA_ADDR_MASK ULL(0x3ffffffff)
257 TsunamiPChip::translatePciToDma(Addr busAddr
)
259 // compare the address to the window base registers
260 uint64_t tbaMask
= 0;
263 uint64_t windowMask
= 0;
264 uint64_t windowBase
= 0;
266 uint64_t pteEntry
= 0;
272 DPRINTF(IdeDisk
, "Translation for bus address: %#x\n", busAddr
);
273 for (int i
= 0; i
< 4; i
++) {
274 DPRINTF(IdeDisk
, "(%d) base:%#x mask:%#x\n",
277 windowBase
= wsba
[i
];
278 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
280 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
281 DPRINTF(IdeDisk
, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
282 i
, windowBase
, windowMask
, (busAddr
& windowMask
),
283 (windowBase
& windowMask
));
288 for (int i
= 0; i
< 4; i
++) {
290 windowBase
= wsba
[i
];
291 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
293 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
295 if (wsba
[i
] & 0x1) { // see if enabled
296 if (wsba
[i
] & 0x2) { // see if SG bit is set
298 This currently is faked by just doing a direct
299 read from memory, however, to be realistic, this
300 needs to actually do a bus transaction. The process
301 is explained in the tsunami documentation on page
302 10-12 and basically munges the address to look up a
303 PTE from a table in memory and then uses that mapping
304 to create an address for the SG page
307 tbaMask
= ~(((wsm
[i
] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
308 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
309 pteAddr
= (tba
[i
] & tbaMask
) | ((busAddr
& baMask
) >> 10);
311 memcpy((void *)&pteEntry
,
313 physmem
->dma_addr(pteAddr
, sizeof(uint64_t)),
316 dmaAddr
= ((pteEntry
& ~ULL(0x1)) << 12) | (busAddr
& ULL(0x1fff));
319 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | ULL(0xfffff);
321 dmaAddr
= (tba
[i
] & tbaMask
) | (busAddr
& baMask
);
324 return (dmaAddr
& DMA_ADDR_MASK
);
329 // if no match was found, then return the original address
334 TsunamiPChip::serialize(std::ostream
&os
)
336 SERIALIZE_SCALAR(pctl
);
337 SERIALIZE_ARRAY(wsba
, 4);
338 SERIALIZE_ARRAY(wsm
, 4);
339 SERIALIZE_ARRAY(tba
, 4);
343 TsunamiPChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
345 UNSERIALIZE_SCALAR(pctl
);
346 UNSERIALIZE_ARRAY(wsba
, 4);
347 UNSERIALIZE_ARRAY(wsm
, 4);
348 UNSERIALIZE_ARRAY(tba
, 4);
352 TsunamiPChip::cacheAccess(MemReqPtr
&req
)
354 return curTick
+ 1000;
357 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
359 SimObjectParam
<Tsunami
*> tsunami
;
360 SimObjectParam
<MemoryController
*> mmu
;
362 SimObjectParam
<Bus
*> io_bus
;
363 SimObjectParam
<HierParams
*> hier
;
365 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
367 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
369 INIT_PARAM(tsunami
, "Tsunami"),
370 INIT_PARAM(mmu
, "Memory Controller"),
371 INIT_PARAM(addr
, "Device Address"),
372 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
373 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
375 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
377 CREATE_SIM_OBJECT(TsunamiPChip
)
379 return new TsunamiPChip(getInstanceName(), tsunami
, addr
, mmu
, hier
, io_bus
);
382 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip
)