11 #include "base/trace.hh"
12 #include "cpu/exec_context.hh"
13 #include "dev/console.hh"
14 #include "dev/etherdev.hh"
15 #include "dev/scsi_ctrl.hh"
16 #include "dev/tlaser_clock.hh"
17 #include "dev/tsunami_pchip.hh"
18 #include "dev/tsunamireg.h"
19 #include "dev/tsunami.hh"
20 #include "mem/functional_mem/memory_control.hh"
21 #include "mem/functional_mem/physical_memory.hh"
22 #include "sim/builder.hh"
23 #include "sim/system.hh"
27 TsunamiPChip::TsunamiPChip(const string
&name
, Tsunami
*t
, Addr a
,
28 MemoryController
*mmu
)
29 : FunctionalMemory(name
), addr(a
), tsunami(t
)
31 mmu
->add_child(this, Range
<Addr
>(addr
, addr
+ size
));
33 for (int i
= 0; i
< 4; i
++) {
39 //Set back pointer in tsunami
40 tsunami
->pchip
= this;
44 TsunamiPChip::read(MemReqPtr
&req
, uint8_t *data
)
46 DPRINTF(Tsunami
, "read va=%#x size=%d\n",
47 req
->vaddr
, req
->size
);
49 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
)) >> 6;
50 // ExecContext *xc = req->xc;
51 // int cpuid = xc->cpu_id;
55 case sizeof(uint64_t):
58 *(uint64_t*)data
= wsba
[0];
61 *(uint64_t*)data
= wsba
[1];
64 *(uint64_t*)data
= wsba
[2];
67 *(uint64_t*)data
= wsba
[3];
70 *(uint64_t*)data
= wsm
[0];
73 *(uint64_t*)data
= wsm
[1];
76 *(uint64_t*)data
= wsm
[2];
79 *(uint64_t*)data
= wsm
[3];
82 *(uint64_t*)data
= tba
[0];
85 *(uint64_t*)data
= tba
[1];
88 *(uint64_t*)data
= tba
[2];
91 *(uint64_t*)data
= tba
[3];
94 // might want to change the clock??
95 *(uint64_t*)data
= 0x00; // try this
98 panic("PC_PLAT not implemented\n");
100 panic("PC_RES not implemented\n");
101 case TSDEV_PC_PERROR
:
102 panic("PC_PERROR not implemented\n");
103 case TSDEV_PC_PERRMASK
:
104 panic("PC_PERRMASK not implemented\n");
105 case TSDEV_PC_PERRSET
:
106 panic("PC_PERRSET not implemented\n");
108 panic("PC_TLBIV not implemented\n");
110 *(uint64_t*)data
= 0x00; // shouldn't be readable, but linux
112 case TSDEV_PC_PMONCTL
:
113 panic("PC_PMONCTL not implemented\n");
114 case TSDEV_PC_PMONCNT
:
115 panic("PC_PMONCTN not implemented\n");
117 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
122 case sizeof(uint32_t):
123 case sizeof(uint16_t):
124 case sizeof(uint8_t):
126 panic("invalid access size(?) for tsunami register!\n\n");
128 DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr
, req
->size
);
134 TsunamiPChip::write(MemReqPtr
&req
, const uint8_t *data
)
136 DPRINTF(Tsunami
, "write - va=%#x size=%d \n",
137 req
->vaddr
, req
->size
);
139 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
)) >> 6;
143 case sizeof(uint64_t):
146 wsba
[0] = *(uint64_t*)data
;
149 wsba
[1] = *(uint64_t*)data
;
152 wsba
[2] = *(uint64_t*)data
;
155 wsba
[3] = *(uint64_t*)data
;
158 wsm
[0] = *(uint64_t*)data
;
161 wsm
[1] = *(uint64_t*)data
;
164 wsm
[2] = *(uint64_t*)data
;
167 wsm
[3] = *(uint64_t*)data
;
170 tba
[0] = *(uint64_t*)data
;
173 tba
[1] = *(uint64_t*)data
;
176 tba
[2] = *(uint64_t*)data
;
179 tba
[3] = *(uint64_t*)data
;
182 // might want to change the clock??
183 //*(uint64_t*)data; // try this
186 panic("PC_PLAT not implemented\n");
188 panic("PC_RES not implemented\n");
189 case TSDEV_PC_PERROR
:
190 panic("PC_PERROR not implemented\n");
191 case TSDEV_PC_PERRMASK
:
192 panic("PC_PERRMASK not implemented\n");
193 case TSDEV_PC_PERRSET
:
194 panic("PC_PERRSET not implemented\n");
196 panic("PC_TLBIV not implemented\n");
198 return No_Fault
; // value ignored, supposted to invalidate SG TLB
199 case TSDEV_PC_PMONCTL
:
200 panic("PC_PMONCTL not implemented\n");
201 case TSDEV_PC_PMONCNT
:
202 panic("PC_PMONCTN not implemented\n");
204 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
209 case sizeof(uint32_t):
210 case sizeof(uint16_t):
211 case sizeof(uint8_t):
213 panic("invalid access size(?) for tsunami register!\n\n");
216 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr
, req
->size
);
221 #define DMA_ADDR_MASK ULL(0x3ffffffff)
224 TsunamiPChip::translatePciToDma(Addr busAddr
)
226 // compare the address to the window base registers
227 uint64_t tbaMask
= 0;
230 uint64_t windowMask
= 0;
231 uint64_t windowBase
= 0;
233 uint64_t pteEntry
= 0;
238 for (int i
= 0; i
< 4; i
++) {
239 windowBase
= wsba
[i
];
240 windowMask
= ~wsm
[i
] & (0x7ff << 20);
242 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
245 if (wsba
[i
] & 0x1) { // see if enabled
246 if (wsba
[i
] & 0x2) { // see if SG bit is set
248 This currently is faked by just doing a direct
249 read from memory, however, to be realistic, this
250 needs to actually do a bus transaction. The process
251 is explained in the tsunami documentation on page
252 10-12 and basically munges the address to look up a
253 PTE from a table in memory and then uses that mapping
254 to create an address for the SG page
257 tbaMask
= ~(((wsm
[i
] & (0x7ff << 20)) >> 10) | 0x3ff);
258 baMask
= (wsm
[i
] & (0x7ff << 20)) | (0x7f << 13);
259 pteAddr
= (tba
[i
] & tbaMask
) | ((busAddr
& baMask
) >> 10);
261 memcpy((void *)&pteEntry
,
263 physmem
->dma_addr(pteAddr
, sizeof(uint64_t)),
266 dmaAddr
= ((pteEntry
& ~0x1) << 12) | (busAddr
& 0x1fff);
269 baMask
= (wsm
[i
] & (0x7ff << 20)) | 0xfffff;
271 dmaAddr
= (tba
[i
] & tbaMask
) | (busAddr
& baMask
);
274 return (dmaAddr
& DMA_ADDR_MASK
);
283 TsunamiPChip::serialize(std::ostream
&os
)
285 SERIALIZE_ARRAY(wsba
, 4);
286 SERIALIZE_ARRAY(wsm
, 4);
287 SERIALIZE_ARRAY(tba
, 4);
291 TsunamiPChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
293 UNSERIALIZE_ARRAY(wsba
, 4);
294 UNSERIALIZE_ARRAY(wsm
, 4);
295 UNSERIALIZE_ARRAY(tba
, 4);
298 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
300 SimObjectParam
<Tsunami
*> tsunami
;
301 SimObjectParam
<MemoryController
*> mmu
;
304 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
306 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
308 INIT_PARAM(tsunami
, "Tsunami"),
309 INIT_PARAM(mmu
, "Memory Controller"),
310 INIT_PARAM(addr
, "Device Address")
312 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
314 CREATE_SIM_OBJECT(TsunamiPChip
)
316 return new TsunamiPChip(getInstanceName(), tsunami
, addr
, mmu
);
319 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip
)