dev/tsunami_pchip.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * Tsunami PChip (pci)
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "base/trace.hh"
  38 #include "cpu/exec_context.hh"
  39 #include "dev/console.hh"
  40 #include "dev/etherdev.hh"
  41 #include "dev/scsi_ctrl.hh"
  42 #include "dev/tlaser_clock.hh"
  43 #include "dev/tsunami_pchip.hh"
  44 #include "dev/tsunamireg.h"
  45 #include "dev/tsunami.hh"
  46 #include "mem/functional_mem/memory_control.hh"
  47 #include "mem/functional_mem/physical_memory.hh"
  48 #include "sim/builder.hh"
  49 #include "sim/system.hh"
  50
  51 using namespace std;
  52
  53 TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
  54                            MemoryController *mmu)
  55     : FunctionalMemory(name), addr(a), tsunami(t)
  56 {
  57     mmu->add_child(this, Range<Addr>(addr, addr + size));
  58
  59     for (int i = 0; i < 4; i++) {
  60         wsba[i] = 0;
  61         wsm[i] = 0;
  62         tba[i] = 0;
  63     }
  64
  65     // initialize pchip control register
  66     pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
  67
  68     //Set back pointer in tsunami
  69     tsunami->pchip = this;
  70 }
  71
  72 Fault
  73 TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
  74 {
  75     DPRINTF(Tsunami, "read  va=%#x size=%d\n",
  76             req->vaddr, req->size);
  77
  78     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
  79
  80     switch (req->size) {
  81
  82       case sizeof(uint64_t):
  83           switch(daddr) {
  84               case TSDEV_PC_WSBA0:
  85                     *(uint64_t*)data = wsba[0];
  86                     return No_Fault;
  87               case TSDEV_PC_WSBA1:
  88                     *(uint64_t*)data = wsba[1];
  89                     return No_Fault;
  90               case TSDEV_PC_WSBA2:
  91                     *(uint64_t*)data = wsba[2];
  92                     return No_Fault;
  93               case TSDEV_PC_WSBA3:
  94                     *(uint64_t*)data = wsba[3];
  95                     return No_Fault;
  96               case TSDEV_PC_WSM0:
  97                     *(uint64_t*)data = wsm[0];
  98                     return No_Fault;
  99               case TSDEV_PC_WSM1:
 100                     *(uint64_t*)data = wsm[1];
 101                     return No_Fault;
 102               case TSDEV_PC_WSM2:
 103                     *(uint64_t*)data = wsm[2];
 104                     return No_Fault;
 105               case TSDEV_PC_WSM3:
 106                     *(uint64_t*)data = wsm[3];
 107                     return No_Fault;
 108               case TSDEV_PC_TBA0:
 109                     *(uint64_t*)data = tba[0];
 110                     return No_Fault;
 111               case TSDEV_PC_TBA1:
 112                     *(uint64_t*)data = tba[1];
 113                     return No_Fault;
 114               case TSDEV_PC_TBA2:
 115                     *(uint64_t*)data = tba[2];
 116                     return No_Fault;
 117               case TSDEV_PC_TBA3:
 118                     *(uint64_t*)data = tba[3];
 119                     return No_Fault;
 120               case TSDEV_PC_PCTL:
 121                     *(uint64_t*)data = pctl;
 122                     return No_Fault;
 123               case TSDEV_PC_PLAT:
 124                     panic("PC_PLAT not implemented\n");
 125               case TSDEV_PC_RES:
 126                     panic("PC_RES not implemented\n");
 127               case TSDEV_PC_PERROR:
 128                     *(uint64_t*)data = 0x00;
 129                     return No_Fault;
 130               case TSDEV_PC_PERRMASK:
 131                     *(uint64_t*)data = 0x00;
 132                     return No_Fault;
 133               case TSDEV_PC_PERRSET:
 134                     panic("PC_PERRSET not implemented\n");
 135               case TSDEV_PC_TLBIV:
 136                     panic("PC_TLBIV not implemented\n");
 137               case TSDEV_PC_TLBIA:
 138                     *(uint64_t*)data = 0x00; // shouldn't be readable, but linux
 139                     return No_Fault;
 140               case TSDEV_PC_PMONCTL:
 141                     panic("PC_PMONCTL not implemented\n");
 142               case TSDEV_PC_PMONCNT:
 143                     panic("PC_PMONCTN not implemented\n");
 144               default:
 145                   panic("Default in PChip Read reached reading 0x%x\n", daddr);
 146
 147            } // uint64_t
 148
 149       break;
 150       case sizeof(uint32_t):
 151       case sizeof(uint16_t):
 152       case sizeof(uint8_t):
 153       default:
 154         panic("invalid access size(?) for tsunami register!\n\n");
 155     }
 156     DPRINTFN("Tsunami PChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
 157
 158     return No_Fault;
 159 }
 160
 161 Fault
 162 TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
 163 {
 164     DPRINTF(Tsunami, "write - va=%#x size=%d \n",
 165             req->vaddr, req->size);
 166
 167     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
 168
 169     switch (req->size) {
 170
 171       case sizeof(uint64_t):
 172           switch(daddr) {
 173               case TSDEV_PC_WSBA0:
 174                     wsba[0] = *(uint64_t*)data;
 175                     return No_Fault;
 176               case TSDEV_PC_WSBA1:
 177                     wsba[1] = *(uint64_t*)data;
 178                     return No_Fault;
 179               case TSDEV_PC_WSBA2:
 180                     wsba[2] = *(uint64_t*)data;
 181                     return No_Fault;
 182               case TSDEV_PC_WSBA3:
 183                     wsba[3] = *(uint64_t*)data;
 184                     return No_Fault;
 185               case TSDEV_PC_WSM0:
 186                     wsm[0] = *(uint64_t*)data;
 187                     return No_Fault;
 188               case TSDEV_PC_WSM1:
 189                     wsm[1] = *(uint64_t*)data;
 190                     return No_Fault;
 191               case TSDEV_PC_WSM2:
 192                     wsm[2] = *(uint64_t*)data;
 193                     return No_Fault;
 194               case TSDEV_PC_WSM3:
 195                     wsm[3] = *(uint64_t*)data;
 196                     return No_Fault;
 197               case TSDEV_PC_TBA0:
 198                     tba[0] = *(uint64_t*)data;
 199                     return No_Fault;
 200               case TSDEV_PC_TBA1:
 201                     tba[1] = *(uint64_t*)data;
 202                     return No_Fault;
 203               case TSDEV_PC_TBA2:
 204                     tba[2] = *(uint64_t*)data;
 205                     return No_Fault;
 206               case TSDEV_PC_TBA3:
 207                     tba[3] = *(uint64_t*)data;
 208                     return No_Fault;
 209               case TSDEV_PC_PCTL:
 210                     pctl = *(uint64_t*)data;
 211                     return No_Fault;
 212               case TSDEV_PC_PLAT:
 213                     panic("PC_PLAT not implemented\n");
 214               case TSDEV_PC_RES:
 215                     panic("PC_RES not implemented\n");
 216               case TSDEV_PC_PERROR:
 217                     return No_Fault;
 218               case TSDEV_PC_PERRMASK:
 219                     panic("PC_PERRMASK not implemented\n");
 220               case TSDEV_PC_PERRSET:
 221                     panic("PC_PERRSET not implemented\n");
 222               case TSDEV_PC_TLBIV:
 223                     panic("PC_TLBIV not implemented\n");
 224               case TSDEV_PC_TLBIA:
 225                     return No_Fault; // value ignored, supposted to invalidate SG TLB
 226               case TSDEV_PC_PMONCTL:
 227                     panic("PC_PMONCTL not implemented\n");
 228               case TSDEV_PC_PMONCNT:
 229                     panic("PC_PMONCTN not implemented\n");
 230               default:
 231                   panic("Default in PChip Read reached reading 0x%x\n", daddr);
 232
 233            } // uint64_t
 234
 235       break;
 236       case sizeof(uint32_t):
 237       case sizeof(uint16_t):
 238       case sizeof(uint8_t):
 239       default:
 240         panic("invalid access size(?) for tsunami register!\n\n");
 241     }
 242
 243     DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
 244
 245     return No_Fault;
 246 }
 247
 248 #define DMA_ADDR_MASK ULL(0x3ffffffff)
 249
 250 Addr
 251 TsunamiPChip::translatePciToDma(Addr busAddr)
 252 {
 253     // compare the address to the window base registers
 254     uint64_t tbaMask = 0;
 255     uint64_t baMask = 0;
 256
 257     uint64_t windowMask = 0;
 258     uint64_t windowBase = 0;
 259
 260     uint64_t pteEntry = 0;
 261
 262     Addr pteAddr;
 263     Addr dmaAddr;
 264
 265 #if 0
 266     DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
 267     for (int i = 0; i < 4; i++) {
 268         DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
 269                 i, wsba[i], wsm[i]);
 270
 271         windowBase = wsba[i];
 272         windowMask = ~wsm[i] & (ULL(0xfff) << 20);
 273
 274         if ((busAddr & windowMask) == (windowBase & windowMask)) {
 275             DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
 276                     i, windowBase, windowMask, (busAddr & windowMask),
 277                     (windowBase & windowMask));
 278         }
 279     }
 280 #endif
 281
 282     for (int i = 0; i < 4; i++) {
 283
 284         windowBase = wsba[i];
 285         windowMask = ~wsm[i] & (ULL(0xfff) << 20);
 286
 287         if ((busAddr & windowMask) == (windowBase & windowMask)) {
 288
 289             if (wsba[i] & 0x1) {   // see if enabled
 290                 if (wsba[i] & 0x2) { // see if SG bit is set
 291                     /** @todo
 292                         This currently is faked by just doing a direct
 293                         read from memory, however, to be realistic, this
 294                         needs to actually do a bus transaction.  The process
 295                         is explained in the tsunami documentation on page
 296                         10-12 and basically munges the address to look up a
 297                         PTE from a table in memory and then uses that mapping
 298                         to create an address for the SG page
 299                     */
 300
 301                     tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
 302                     baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
 303                     pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
 304
 305                     memcpy((void *)&pteEntry,
 306                            tsunami->system->
 307                            physmem->dma_addr(pteAddr, sizeof(uint64_t)),
 308                            sizeof(uint64_t));
 309
 310                     dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
 311
 312                 } else {
 313                     baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
 314                     tbaMask = ~baMask;
 315                     dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
 316                 }
 317
 318                 return (dmaAddr & DMA_ADDR_MASK);
 319             }
 320         }
 321     }
 322
 323     // if no match was found, then return the original address
 324     return busAddr;
 325 }
 326
 327 void
 328 TsunamiPChip::serialize(std::ostream &os)
 329 {
 330     SERIALIZE_SCALAR(pctl);
 331     SERIALIZE_ARRAY(wsba, 4);
 332     SERIALIZE_ARRAY(wsm, 4);
 333     SERIALIZE_ARRAY(tba, 4);
 334 }
 335
 336 void
 337 TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
 338 {
 339     UNSERIALIZE_SCALAR(pctl);
 340     UNSERIALIZE_ARRAY(wsba, 4);
 341     UNSERIALIZE_ARRAY(wsm, 4);
 342     UNSERIALIZE_ARRAY(tba, 4);
 343 }
 344
 345 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
 346
 347     SimObjectParam<Tsunami *> tsunami;
 348     SimObjectParam<MemoryController *> mmu;
 349     Param<Addr> addr;
 350
 351 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
 352
 353 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
 354
 355     INIT_PARAM(tsunami, "Tsunami"),
 356     INIT_PARAM(mmu, "Memory Controller"),
 357     INIT_PARAM(addr, "Device Address")
 358
 359 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
 360
 361 CREATE_SIM_OBJECT(TsunamiPChip)
 362 {
 363     return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu);
 364 }
 365
 366 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)