2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include "base/trace.hh"
38 #include "dev/tsunami_pchip.hh"
39 #include "dev/tsunamireg.h"
40 #include "dev/tsunami.hh"
41 #include "mem/bus/bus.hh"
42 #include "mem/bus/pio_interface.hh"
43 #include "mem/bus/pio_interface_impl.hh"
44 #include "mem/functional_mem/memory_control.hh"
45 #include "mem/functional_mem/physical_memory.hh"
46 #include "sim/builder.hh"
47 #include "sim/system.hh"
51 TsunamiPChip::TsunamiPChip(const string
&name
, Tsunami
*t
, Addr a
,
52 MemoryController
*mmu
, HierParams
*hier
,
53 Bus
*bus
, Tick pio_latency
)
54 : PioDevice(name
, t
), addr(a
), tsunami(t
)
56 mmu
->add_child(this, RangeSize(addr
, size
));
58 for (int i
= 0; i
< 4; i
++) {
65 pioInterface
= newPioInterface(name
, hier
, bus
, this,
66 &TsunamiPChip::cacheAccess
);
67 pioInterface
->addAddrRange(RangeSize(addr
, size
));
68 pioLatency
= pio_latency
* bus
->clockRatio
;
72 // initialize pchip control register
73 pctl
= (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
75 //Set back pointer in tsunami
76 tsunami
->pchip
= this;
80 TsunamiPChip::read(MemReqPtr
&req
, uint8_t *data
)
82 DPRINTF(Tsunami
, "read va=%#x size=%d\n",
83 req
->vaddr
, req
->size
);
85 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
)) >> 6;
89 case sizeof(uint64_t):
92 *(uint64_t*)data
= wsba
[0];
95 *(uint64_t*)data
= wsba
[1];
98 *(uint64_t*)data
= wsba
[2];
101 *(uint64_t*)data
= wsba
[3];
104 *(uint64_t*)data
= wsm
[0];
107 *(uint64_t*)data
= wsm
[1];
110 *(uint64_t*)data
= wsm
[2];
113 *(uint64_t*)data
= wsm
[3];
116 *(uint64_t*)data
= tba
[0];
119 *(uint64_t*)data
= tba
[1];
122 *(uint64_t*)data
= tba
[2];
125 *(uint64_t*)data
= tba
[3];
128 *(uint64_t*)data
= pctl
;
131 panic("PC_PLAT not implemented\n");
133 panic("PC_RES not implemented\n");
134 case TSDEV_PC_PERROR
:
135 *(uint64_t*)data
= 0x00;
137 case TSDEV_PC_PERRMASK
:
138 *(uint64_t*)data
= 0x00;
140 case TSDEV_PC_PERRSET
:
141 panic("PC_PERRSET not implemented\n");
143 panic("PC_TLBIV not implemented\n");
145 *(uint64_t*)data
= 0x00; // shouldn't be readable, but linux
147 case TSDEV_PC_PMONCTL
:
148 panic("PC_PMONCTL not implemented\n");
149 case TSDEV_PC_PMONCNT
:
150 panic("PC_PMONCTN not implemented\n");
152 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
157 case sizeof(uint32_t):
158 case sizeof(uint16_t):
159 case sizeof(uint8_t):
161 panic("invalid access size(?) for tsunami register!\n\n");
163 DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr
, req
->size
);
169 TsunamiPChip::write(MemReqPtr
&req
, const uint8_t *data
)
171 DPRINTF(Tsunami
, "write - va=%#x size=%d \n",
172 req
->vaddr
, req
->size
);
174 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
)) >> 6;
178 case sizeof(uint64_t):
181 wsba
[0] = *(uint64_t*)data
;
184 wsba
[1] = *(uint64_t*)data
;
187 wsba
[2] = *(uint64_t*)data
;
190 wsba
[3] = *(uint64_t*)data
;
193 wsm
[0] = *(uint64_t*)data
;
196 wsm
[1] = *(uint64_t*)data
;
199 wsm
[2] = *(uint64_t*)data
;
202 wsm
[3] = *(uint64_t*)data
;
205 tba
[0] = *(uint64_t*)data
;
208 tba
[1] = *(uint64_t*)data
;
211 tba
[2] = *(uint64_t*)data
;
214 tba
[3] = *(uint64_t*)data
;
217 pctl
= *(uint64_t*)data
;
220 panic("PC_PLAT not implemented\n");
222 panic("PC_RES not implemented\n");
223 case TSDEV_PC_PERROR
:
225 case TSDEV_PC_PERRMASK
:
226 panic("PC_PERRMASK not implemented\n");
227 case TSDEV_PC_PERRSET
:
228 panic("PC_PERRSET not implemented\n");
230 panic("PC_TLBIV not implemented\n");
232 return No_Fault
; // value ignored, supposted to invalidate SG TLB
233 case TSDEV_PC_PMONCTL
:
234 panic("PC_PMONCTL not implemented\n");
235 case TSDEV_PC_PMONCNT
:
236 panic("PC_PMONCTN not implemented\n");
238 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
243 case sizeof(uint32_t):
244 case sizeof(uint16_t):
245 case sizeof(uint8_t):
247 panic("invalid access size(?) for tsunami register!\n\n");
250 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr
, req
->size
);
255 #define DMA_ADDR_MASK ULL(0x3ffffffff)
258 TsunamiPChip::translatePciToDma(Addr busAddr
)
260 // compare the address to the window base registers
261 uint64_t tbaMask
= 0;
264 uint64_t windowMask
= 0;
265 uint64_t windowBase
= 0;
267 uint64_t pteEntry
= 0;
273 DPRINTF(IdeDisk
, "Translation for bus address: %#x\n", busAddr
);
274 for (int i
= 0; i
< 4; i
++) {
275 DPRINTF(IdeDisk
, "(%d) base:%#x mask:%#x\n",
278 windowBase
= wsba
[i
];
279 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
281 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
282 DPRINTF(IdeDisk
, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
283 i
, windowBase
, windowMask
, (busAddr
& windowMask
),
284 (windowBase
& windowMask
));
289 for (int i
= 0; i
< 4; i
++) {
291 windowBase
= wsba
[i
];
292 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
294 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
296 if (wsba
[i
] & 0x1) { // see if enabled
297 if (wsba
[i
] & 0x2) { // see if SG bit is set
299 This currently is faked by just doing a direct
300 read from memory, however, to be realistic, this
301 needs to actually do a bus transaction. The process
302 is explained in the tsunami documentation on page
303 10-12 and basically munges the address to look up a
304 PTE from a table in memory and then uses that mapping
305 to create an address for the SG page
308 tbaMask
= ~(((wsm
[i
] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
309 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
310 pteAddr
= (tba
[i
] & tbaMask
) | ((busAddr
& baMask
) >> 10);
312 memcpy((void *)&pteEntry
,
314 physmem
->dma_addr(pteAddr
, sizeof(uint64_t)),
317 dmaAddr
= ((pteEntry
& ~ULL(0x1)) << 12) | (busAddr
& ULL(0x1fff));
320 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | ULL(0xfffff);
322 dmaAddr
= (tba
[i
] & tbaMask
) | (busAddr
& baMask
);
325 return (dmaAddr
& DMA_ADDR_MASK
);
330 // if no match was found, then return the original address
335 TsunamiPChip::serialize(std::ostream
&os
)
337 SERIALIZE_SCALAR(pctl
);
338 SERIALIZE_ARRAY(wsba
, 4);
339 SERIALIZE_ARRAY(wsm
, 4);
340 SERIALIZE_ARRAY(tba
, 4);
344 TsunamiPChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
346 UNSERIALIZE_SCALAR(pctl
);
347 UNSERIALIZE_ARRAY(wsba
, 4);
348 UNSERIALIZE_ARRAY(wsm
, 4);
349 UNSERIALIZE_ARRAY(tba
, 4);
353 TsunamiPChip::cacheAccess(MemReqPtr
&req
)
355 return curTick
+ pioLatency
;
358 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
360 SimObjectParam
<Tsunami
*> tsunami
;
361 SimObjectParam
<MemoryController
*> mmu
;
363 SimObjectParam
<Bus
*> io_bus
;
364 Param
<Tick
> pio_latency
;
365 SimObjectParam
<HierParams
*> hier
;
367 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip
)
369 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
371 INIT_PARAM(tsunami
, "Tsunami"),
372 INIT_PARAM(mmu
, "Memory Controller"),
373 INIT_PARAM(addr
, "Device Address"),
374 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
375 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
376 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
378 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip
)
380 CREATE_SIM_OBJECT(TsunamiPChip
)
382 return new TsunamiPChip(getInstanceName(), tsunami
, addr
, mmu
, hier
,
383 io_bus
, pio_latency
);
386 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip
)