dev/tsunami_pchip.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Tsunami PCI interface CSRs
  31  */
  32
  33 #ifndef __TSUNAMI_PCHIP_HH__
  34 #define __TSUNAMI_PCHIP_HH__
  35
  36 #include "dev/tsunami.hh"
  37 #include "base/range.hh"
  38 #include "dev/io_device.hh"
  39
  40 class MemoryController;
  41
  42 /**
  43  * A very simple implementation of the Tsunami PCI interface chips.
  44  */
  45 class TsunamiPChip : public PioDevice
  46 {
  47   private:
  48     /** The base address of this device */
  49     Addr addr;
  50
  51     /** The size of mappad from the above address */
  52     static const Addr size = 0xfff;
  53
  54   protected:
  55     /**
  56      * pointer to the tsunami object.
  57      * This is our access to all the other tsunami
  58      * devices.
  59      */
  60     Tsunami *tsunami;
  61
  62     /** Pchip control register */
  63     uint64_t pctl;
  64
  65     /** Window Base addresses */
  66     uint64_t wsba[4];
  67
  68     /** Window masks */
  69     uint64_t wsm[4];
  70
  71     /** Translated Base Addresses */
  72     uint64_t tba[4];
  73
  74   public:
  75     /**
  76      * Register the PChip with the mmu and init all wsba, wsm, and tba to 0
  77      * @param name the name of thes device
  78      * @param t a pointer to the tsunami device
  79      * @param a the address which we respond to
  80      * @param mmu the mmu we are to register with
  81      * @param hier object to store parameters universal the device hierarchy
  82      * @param bus The bus that this device is attached to
  83      */
  84     TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
  85                  MemoryController *mmu, HierParams *hier, Bus *bus,
  86                  Tick pio_latency);
  87
  88     /**
  89      * Translate a PCI bus address to a memory address for DMA.
  90      * @todo Andrew says this needs to be fixed. What's wrong with it?
  91      * @param busAddr PCI address to translate.
  92      * @return memory system address
  93      */
  94     Addr translatePciToDma(Addr busAddr);
  95
  96      /**
  97       * Process a read to the PChip.
  98       * @param req Contains the address to read from.
  99       * @param data A pointer to write the read data to.
 100       * @return The fault condition of the access.
 101       */
 102     virtual Fault read(MemReqPtr &req, uint8_t *data);
 103
 104     /**
 105       * Process a write to the PChip.
 106       * @param req Contains the address to write to.
 107       * @param data The data to write.
 108       * @return The fault condition of the access.
 109       */
 110     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 111
 112     /**
 113      * Serialize this object to the given output stream.
 114      * @param os The stream to serialize to.
 115      */
 116     virtual void serialize(std::ostream &os);
 117
 118     /**
 119      * Reconstruct the state of this object from a checkpoint.
 120      * @param cp The checkpoint use.
 121      * @param section The section name of this object
 122      */
 123     virtual void unserialize(Checkpoint *cp, const std::string &section);
 124
 125     /**
 126      * Return how long this access will take.
 127      * @param req the memory request to calcuate
 128      * @return Tick when the request is done
 129      */
 130     Tick cacheAccess(MemReqPtr &req);
 131 };
 132
 133 #endif // __TSUNAMI_PCHIP_HH__