Merge saidi@zizzer:/z/m5/Bitkeeper/m5/
[gem5.git] / dev / tsunami_uart.hh
1 /*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /* @file
30 * Tsunami UART
31 */
32
33 #ifndef __TSUNAMI_UART_HH__
34 #define __TSUNAMI_UART_HH__
35
36 #include "dev/tsunamireg.h"
37 #include "base/range.hh"
38 #include "dev/io_device.hh"
39
40 class SimConsole;
41
42 /*
43 * Tsunami UART
44 */
45 class TsunamiUart : public PioDevice
46 {
47 private:
48 Addr addr;
49 static const Addr size = 0x8;
50
51
52 protected:
53 SimConsole *cons;
54 int status_store;
55 uint8_t next_char;
56 bool valid_char;
57 uint8_t IER;
58
59 class IntrEvent : public Event
60 {
61 protected:
62 TsunamiUart *uart;
63 public:
64 IntrEvent(TsunamiUart *u);
65 virtual void process();
66 virtual const char *description();
67 void scheduleIntr();
68 };
69
70 IntrEvent intrEvent;
71
72 public:
73 TsunamiUart(const string &name, SimConsole *c, MemoryController *mmu,
74 Addr a, HierParams *hier, Bus *bus);
75
76 Fault read(MemReqPtr &req, uint8_t *data);
77 Fault write(MemReqPtr &req, const uint8_t *data);
78
79
80 virtual void serialize(std::ostream &os);
81 virtual void unserialize(Checkpoint *cp, const std::string &section);
82
83 public:
84 Tick cacheAccess(MemReqPtr &req);
85 };
86
87 #endif // __TSUNAMI_UART_HH__