dev/tsunamireg.h

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __TSUNAMIREG_H__
  30 #define __TSUNAMIREG_H__
  31
  32 #define ALPHA_K0SEG_BASE  ULL(0xfffffc0000000000)
  33
  34 // CChip Registers
  35 #define TSDEV_CC_CSR    0x00
  36 #define TSDEV_CC_MTR    0x01
  37 #define TSDEV_CC_MISC   0x02
  38
  39 #define TSDEV_CC_AAR0   0x04
  40 #define TSDEV_CC_AAR1   0x05
  41 #define TSDEV_CC_AAR2   0x06
  42 #define TSDEV_CC_AAR3   0x07
  43 #define TSDEV_CC_DIM0   0x08
  44 #define TSDEV_CC_DIM1   0x09
  45 #define TSDEV_CC_DIR0   0x0A
  46 #define TSDEV_CC_DIR1   0x0B
  47 #define TSDEV_CC_DRIR   0x0C
  48 #define TSDEV_CC_PRBEN  0x0D
  49 #define TSDEV_CC_IIC0   0x0E
  50 #define TSDEV_CC_IIC1   0x0F
  51 #define TSDEV_CC_MPR0   0x10
  52 #define TSDEV_CC_MPR1   0x11
  53 #define TSDEV_CC_MPR2   0x12
  54 #define TSDEV_CC_MPR3   0x13
  55
  56 #define TSDEV_CC_DIM2   0x18
  57 #define TSDEV_CC_DIM3   0x19
  58 #define TSDEV_CC_DIR2   0x1A
  59 #define TSDEV_CC_DIR3   0x1B
  60 #define TSDEV_CC_IIC2   0x1C
  61 #define TSDEV_CC_IIC3   0x1D
  62
  63
  64 // PChip Registers
  65 #define TSDEV_PC_WSBA0      0x00
  66 #define TSDEV_PC_WSBA1      0x01
  67 #define TSDEV_PC_WSBA2      0x02
  68 #define TSDEV_PC_WSBA3      0x03
  69 #define TSDEV_PC_WSM0       0x04
  70 #define TSDEV_PC_WSM1       0x05
  71 #define TSDEV_PC_WSM2       0x06
  72 #define TSDEV_PC_WSM3       0x07
  73 #define TSDEV_PC_TBA0       0x08
  74 #define TSDEV_PC_TBA1       0x09
  75 #define TSDEV_PC_TBA2       0x0A
  76 #define TSDEV_PC_TBA3       0x0B
  77 #define TSDEV_PC_PCTL       0x0C
  78 #define TSDEV_PC_PLAT       0x0D
  79 #define TSDEV_PC_RES        0x0E
  80 #define TSDEV_PC_PERROR     0x0F
  81 #define TSDEV_PC_PERRMASK   0x10
  82 #define TSDEV_PC_PERRSET    0x11
  83 #define TSDEV_PC_TLBIV      0x12
  84 #define TSDEV_PC_TLBIA      0x13
  85 #define TSDEV_PC_PMONCTL    0x14
  86 #define TSDEV_PC_PMONCNT    0x15
  87
  88 #define TSDEV_PC_SPST       0x20
  89
  90
  91 // DChip Registers
  92 #define TSDEV_DC_DSC        0x20
  93 #define TSDEV_DC_STR        0x21
  94 #define TSDEV_DC_DREV       0x22
  95 #define TSDEV_DC_DSC2       0x23
  96
  97 // I/O Ports
  98 #define TSDEV_PIC1_MASK     0x21
  99 #define TSDEV_PIC2_MASK     0xA1
 100 #define TSDEV_PIC1_ISR      0x20
 101 #define TSDEV_PIC2_ISR      0xA0
 102 #define TSDEV_PIC1_ACK      0x20
 103 #define TSDEV_PIC2_ACK      0xA0
 104 #define TSDEV_DMA1_RESET    0x0D
 105 #define TSDEV_DMA2_RESET    0xDA
 106 #define TSDEV_DMA1_MODE     0x0B
 107 #define TSDEV_DMA2_MODE     0xD6
 108 #define TSDEV_DMA1_MASK     0x0A
 109 #define TSDEV_DMA2_MASK     0xD4
 110 #define TSDEV_TMR_CTL       0x61
 111 #define TSDEV_TMR2_CTL      0x43
 112 #define TSDEV_TMR2_DATA     0x42
 113 #define TSDEV_TMR0_DATA     0x40
 114
 115 #define TSDEV_RTC_ADDR      0x70
 116 #define TSDEV_RTC_DATA      0x71
 117
 118 // RTC defines
 119 #define RTC_SECOND          0   // second of minute [0..59]
 120 #define RTC_SECOND_ALARM    1   // seconds to alarm
 121 #define RTC_MINUTE          2   // minute of hour [0..59]
 122 #define RTC_MINUTE_ALARM    3   // minutes to alarm
 123 #define RTC_HOUR            4   // hour of day [0..23]
 124 #define RTC_HOUR_ALARM      5   // hours to alarm
 125 #define RTC_DAY_OF_WEEK     6   // day of week [1..7]
 126 #define RTC_DAY_OF_MONTH    7   // day of month [1..31]
 127 #define RTC_MONTH           8   // month of year [1..12]
 128 #define RTC_YEAR            9   // year [00..99]
 129 #define RTC_CONTROL_REGISTERA   10      // control register A
 130 #define RTC_CONTROL_REGISTERB   11      // control register B
 131 #define RTC_CONTROL_REGISTERC   12      // control register C
 132 #define RTC_CONTROL_REGISTERD   13      // control register D
 133 #define RTC_REGNUMBER_RTC_CR1   0x6A    // control register 1
 134
 135 #define PCHIP_PCI0_MEMORY       ULL(0x00000000000)
 136 #define PCHIP_PCI0_IO           ULL(0x001FC000000)
 137 #define TSUNAMI_UNCACHABLE_BIT  ULL(0x80000000000)
 138 #define TSUNAMI_PCI0_MEMORY     TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY
 139 #define TSUNAMI_PCI0_IO         TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
 140
 141
 142 // UART Defines
 143 #define UART_IER_RDI            0x01
 144 #define UART_IER_THRI           0x02
 145 #define UART_IER_RLSI           0x04
 146
 147
 148 #define UART_LSR_TEMT   0x40
 149 #define UART_LSR_THRE   0x20
 150 #define UART_LSR_DR     0x01
 151
 152 #define UART_MCR_LOOP   0x10
 153
 154 #endif // __TSUNAMIREG_H__