dev/tsunamireg.h

   1
   2 #ifndef __TSUNAMIREG_H__
   3 #define __TSUNAMIREG_H__
   4
   5 #define ALPHA_K0SEG_BASE  0xfffffc0000000000ULL
   6
   7 // CChip Registers
   8 #define TSDEV_CC_CSR    0x00
   9 #define TSDEV_CC_MTR    0x01
  10 #define TSDEV_CC_MISC   0x02
  11
  12 #define TSDEV_CC_AAR0   0x04
  13 #define TSDEV_CC_AAR1   0x05
  14 #define TSDEV_CC_AAR2   0x06
  15 #define TSDEV_CC_AAR3   0x07
  16 #define TSDEV_CC_DIM0   0x08
  17 #define TSDEV_CC_DIM1   0x09
  18 #define TSDEV_CC_DIR0   0x0A
  19 #define TSDEV_CC_DIR1   0x0B
  20 #define TSDEV_CC_DRIR   0x0C
  21 #define TSDEV_CC_PRBEN  0x0D
  22 #define TSDEV_CC_IIC0   0x0E
  23 #define TSDEV_CC_IIC1   0x0F
  24 #define TSDEV_CC_MPR0   0x10
  25 #define TSDEV_CC_MPR1   0x11
  26 #define TSDEV_CC_MPR2   0x12
  27 #define TSDEV_CC_MPR3   0x13
  28
  29 #define TSDEV_CC_DIM2   0x18
  30 #define TSDEV_CC_DIM3   0x19
  31 #define TSDEV_CC_DIR2   0x1A
  32 #define TSDEV_CC_DIR3   0x1B
  33 #define TSDEV_CC_IIC2   0x1C
  34 #define TSDEV_CC_IIC3   0x1D
  35
  36
  37 // PChip Registers
  38 #define TSDEV_PC_WSBA0      0x00
  39 #define TSDEV_PC_WSBA1      0x01
  40 #define TSDEV_PC_WSBA2      0x02
  41 #define TSDEV_PC_WSBA3      0x03
  42 #define TSDEV_PC_WSM0       0x04
  43 #define TSDEV_PC_WSM1       0x05
  44 #define TSDEV_PC_WSM2       0x06
  45 #define TSDEV_PC_WSM3       0x07
  46 #define TSDEV_PC_TBA0       0x08
  47 #define TSDEV_PC_TBA1       0x09
  48 #define TSDEV_PC_TBA2       0x0A
  49 #define TSDEV_PC_TBA3       0x0B
  50 #define TSDEV_PC_PCTL       0x0C
  51 #define TSDEV_PC_PLAT       0x0D
  52 #define TSDEV_PC_RES        0x0E
  53 #define TSDEV_PC_PERROR     0x0F
  54 #define TSDEV_PC_PERRMASK   0x10
  55 #define TSDEV_PC_PERRSET    0x11
  56 #define TSDEV_PC_TLBIV      0x12
  57 #define TSDEV_PC_TLBIA      0x13
  58 #define TSDEV_PC_PMONCTL    0x14
  59 #define TSDEV_PC_PMONCNT    0x15
  60
  61 #define TSDEV_PC_SPST       0x20
  62
  63
  64 // DChip Registers
  65 #define TSDEV_DC_DSC        0x20
  66 #define TSDEV_DC_STR        0x21
  67 #define TSDEV_DC_DREV       0x22
  68 #define TSDEV_DC_DSC2       0x23
  69
  70 // I/O Ports
  71 #define TSDEV_PIC1_MASK     0x21
  72 #define TSDEV_PIC2_MASK     0xA1
  73 #define TSDEV_PIC1_ISR      0x20
  74 #define TSDEV_PIC2_ISR      0xA0
  75 #define TSDEV_PIC1_ACK      0x20
  76 #define TSDEV_PIC2_ACK      0xA0
  77 #define TSDEV_DMA1_RESET    0x0D
  78 #define TSDEV_DMA2_RESET    0xDA
  79 #define TSDEV_DMA1_MODE     0x0B
  80 #define TSDEV_DMA2_MODE     0xD6
  81 #define TSDEV_DMA1_MASK     0x0A
  82 #define TSDEV_DMA2_MASK     0xD4
  83 #define TSDEV_TMR_CTL       0x61
  84 #define TSDEV_TMR2_CTL      0x43
  85 #define TSDEV_TMR2_DATA     0x42
  86 #define TSDEV_TMR0_DATA     0x40
  87
  88 #define TSDEV_RTC_ADDR      0x70
  89 #define TSDEV_RTC_DATA      0x71
  90
  91 // RTC defines
  92 #define RTC_SECOND          0   // second of minute [0..59]
  93 #define RTC_SECOND_ALARM    1   // seconds to alarm
  94 #define RTC_MINUTE          2   // minute of hour [0..59]
  95 #define RTC_MINUTE_ALARM    3   // minutes to alarm
  96 #define RTC_HOUR            4   // hour of day [0..23]
  97 #define RTC_HOUR_ALARM      5   // hours to alarm
  98 #define RTC_DAY_OF_WEEK     6   // day of week [1..7]
  99 #define RTC_DAY_OF_MONTH    7   // day of month [1..31]
 100 #define RTC_MONTH           8   // month of year [1..12]
 101 #define RTC_YEAR            9   // year [00..99]
 102 #define RTC_CONTROL_REGISTERA   10      // control register A
 103 #define RTC_CONTROL_REGISTERB   11      // control register B
 104 #define RTC_CONTROL_REGISTERC   12      // control register C
 105 #define RTC_CONTROL_REGISTERD   13      // control register D
 106 #define RTC_REGNUMBER_RTC_CR1   0x6A    // control register 1
 107
 108 #define PCHIP_PCI0_MEMORY       ULL(0x10000000000)
 109 #define PCHIP_PCI0_IO           ULL(0x101FC000000)
 110 #define TSUNAMI_PCI0_MEMORY     ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY
 111 #define TSUNAMI_PCI0_IO         ALPHA_K0SEG_BASE + PCHIP_PCI0_IO
 112
 113
 114 // UART Defines
 115
 116
 117 #define UART_IER_THRI           0x02
 118 #define UART_IER_RLSI           0x04
 119
 120 #endif // __TSUNAMIREG_H__