dev/uart.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * Implements a 8250 UART
  31  */
  32
  33 #include <string>
  34 #include <vector>
  35
  36 #include "base/inifile.hh"
  37 #include "base/str.hh"        // for to_number
  38 #include "base/trace.hh"
  39 #include "dev/simconsole.hh"
  40 #include "dev/uart.hh"
  41 #include "dev/platform.hh"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/pio_interface.hh"
  44 #include "mem/bus/pio_interface_impl.hh"
  45 #include "mem/functional_mem/memory_control.hh"
  46 #include "sim/builder.hh"
  47
  48 using namespace std;
  49
  50 Uart::IntrEvent::IntrEvent(Uart *u, int bit)
  51     : Event(&mainEventQueue), uart(u)
  52 {
  53     DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
  54     intrBit = bit;
  55 }
  56
  57 const char *
  58 Uart::IntrEvent::description()
  59 {
  60     return "uart interrupt delay event";
  61 }
  62
  63 void
  64 Uart::IntrEvent::process()
  65 {
  66     if (intrBit & uart->IER) {
  67        DPRINTF(Uart, "UART InterEvent, interrupting\n");
  68        uart->platform->postConsoleInt();
  69        uart->status |= intrBit;
  70     }
  71     else
  72        DPRINTF(Uart, "UART InterEvent, not interrupting\n");
  73
  74 }
  75
  76 void
  77 Uart::IntrEvent::scheduleIntr()
  78 {
  79     DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
  80             curTick + (ticksPerSecond/2000) * 350);
  81     if (!scheduled())
  82         /* @todo Make this cleaner, will be much easier with
  83          *       nanosecond time everywhere. Hint hint  Nate. */
  84         schedule(curTick + (ticksPerSecond/2000000000) * 450);
  85     else
  86         reschedule(curTick + (ticksPerSecond/2000000000) * 450);
  87 }
  88
  89 Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
  90            Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
  91     : PioDevice(name, p), addr(a), size(s), cons(c),
  92       txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
  93 {
  94     mmu->add_child(this, RangeSize(addr, size));
  95
  96
  97     if (bus) {
  98         pioInterface = newPioInterface(name, hier, bus, this,
  99                                       &Uart::cacheAccess);
 100         pioInterface->addAddrRange(RangeSize(addr, size));
 101         pioLatency = pio_latency * bus->clockRatio;
 102     }
 103
 104     readAddr = 0;
 105     IER = 0;
 106     DLAB = 0;
 107     LCR = 0;
 108     MCR = 0;
 109     status = 0;
 110
 111     // set back pointers
 112     cons->uart = this;
 113     platform->uart = this;
 114
 115 }
 116
 117 Fault
 118 Uart::read(MemReqPtr &req, uint8_t *data)
 119 {
 120     Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
 121     DPRINTF(Uart, " read register %#x\n", daddr);
 122
 123
 124
 125 #ifdef ALPHA_TLASER
 126
 127     switch (req->size) {
 128       case sizeof(uint64_t):
 129         *(uint64_t *)data = 0;
 130         break;
 131       case sizeof(uint32_t):
 132         *(uint32_t *)data = 0;
 133         break;
 134       case sizeof(uint16_t):
 135         *(uint16_t *)data = 0;
 136         break;
 137       case sizeof(uint8_t):
 138         *(uint8_t *)data = 0;
 139         break;
 140     }
 141
 142     switch (daddr) {
 143       case 0x80: // Status Register
 144         if (readAddr == 3) {
 145             readAddr = 0;
 146             if (status & TX_INT)
 147                 *data = (1 << 4);
 148              else if (status & RX_INT)
 149                 *data = (1 << 5);
 150              else
 151                 DPRINTF(Uart, "spurious read\n");
 152
 153         } else {
 154             *data = (1 << 2);
 155             if (status & RX_INT)
 156                 *data |= (1 << 0);
 157         }
 158         break;
 159
 160       case 0xc0: // Data register (RX)
 161         if (!cons->dataAvailable())
 162             panic("No data to read");
 163
 164         cons->in(*data);
 165
 166         if (!cons->dataAvailable()) {
 167             platform->clearConsoleInt();
 168             status &= ~RX_INT;
 169         }
 170
 171         DPRINTF(Uart, "read data register \'%c\' %2x\n",
 172                 isprint(*data) ? *data : ' ', *data);
 173         break;
 174     }
 175
 176
 177 #else
 178
 179
 180     assert(req->size == 1);
 181
 182     switch (daddr) {
 183         case 0x0:
 184             if (!(LCR & 0x80)) { // read byte
 185                 if (cons->dataAvailable())
 186                     cons->in(*data);
 187                 else {
 188                     *(uint8_t*)data = 0;
 189                     // A limited amount of these are ok.
 190                     DPRINTF(Uart, "empty read of RX register\n");
 191                 }
 192                 status &= ~RX_INT;
 193                 platform->clearConsoleInt();
 194
 195                 if (cons->dataAvailable() && (IER & UART_IER_RDI))
 196                     rxIntrEvent.scheduleIntr();
 197             } else { // dll divisor latch
 198                ;
 199             }
 200             break;
 201         case 0x1:
 202             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 203                 *(uint8_t*)data = IER;
 204             } else { // DLM divisor latch MSB
 205                 ;
 206             }
 207             break;
 208         case 0x2: // Intr Identification Register (IIR)
 209             DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
 210             if (status)
 211                 *(uint8_t*)data = 0;
 212             else
 213                 *(uint8_t*)data = 1;
 214             break;
 215         case 0x3: // Line Control Register (LCR)
 216             *(uint8_t*)data = LCR;
 217             break;
 218         case 0x4: // Modem Control Register (MCR)
 219             break;
 220         case 0x5: // Line Status Register (LSR)
 221             uint8_t lsr;
 222             lsr = 0;
 223             // check if there are any bytes to be read
 224             if (cons->dataAvailable())
 225                 lsr = UART_LSR_DR;
 226             lsr |= UART_LSR_TEMT | UART_LSR_THRE;
 227             *(uint8_t*)data = lsr;
 228             break;
 229         case 0x6: // Modem Status Register (MSR)
 230             *(uint8_t*)data = 0;
 231             break;
 232         case 0x7: // Scratch Register (SCR)
 233             *(uint8_t*)data = 0; // doesn't exist with at 8250.
 234             break;
 235         default:
 236             panic("Tried to access a UART port that doesn't exist\n");
 237             break;
 238     }
 239
 240 #endif
 241     return No_Fault;
 242
 243 }
 244
 245 Fault
 246 Uart::write(MemReqPtr &req, const uint8_t *data)
 247 {
 248     Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
 249
 250     DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
 251
 252 #ifdef ALPHA_TLASER
 253
 254     switch (daddr) {
 255       case 0x80:
 256         readAddr = *data;
 257         switch (*data) {
 258           case 0x28: // Ack of TX
 259               if ((status & TX_INT) == 0)
 260                   panic("Ack of transmit, though there was no interrupt");
 261
 262               status &= ~TX_INT;
 263               platform->clearConsoleInt();
 264               break;
 265           case 0x00:
 266           case 0x01:
 267           case 0x03: // going to read RR3
 268           case 0x12:
 269                 break;
 270           default:
 271                 DPRINTF(Uart, "writing status register %#x \n",
 272                         *(uint64_t *)data);
 273                 break;
 274         }
 275         break;
 276
 277       case 0xc0: // Data register (TX)
 278         cons->out(*(uint64_t *)data);
 279         platform->postConsoleInt();
 280         status |= TX_INT;
 281         break;
 282     }
 283
 284
 285 #else
 286     switch (daddr) {
 287         case 0x0:
 288             if (!(LCR & 0x80)) { // write byte
 289                 cons->out(*(uint8_t *)data);
 290                 platform->clearConsoleInt();
 291                 status &= ~TX_INT;
 292                 if (UART_IER_THRI & IER)
 293                     txIntrEvent.scheduleIntr();
 294             } else { // dll divisor latch
 295                ;
 296             }
 297             break;
 298         case 0x1:
 299             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 300                 IER = *(uint8_t*)data;
 301                 if (UART_IER_THRI & IER)
 302                 {
 303                     DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
 304                     txIntrEvent.scheduleIntr();
 305                 }
 306                 else
 307                 {
 308                     DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
 309                     if (txIntrEvent.scheduled())
 310                         txIntrEvent.deschedule();
 311                     if (status & TX_INT)
 312                         platform->clearConsoleInt();
 313                     status &= ~TX_INT;
 314                 }
 315
 316                 if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
 317                     DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
 318                     rxIntrEvent.scheduleIntr();
 319                 } else {
 320                     DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
 321                     if (rxIntrEvent.scheduled())
 322                         rxIntrEvent.deschedule();
 323                     if (status & RX_INT)
 324                         platform->clearConsoleInt();
 325                     status &= ~RX_INT;
 326                 }
 327              } else { // DLM divisor latch MSB
 328                 ;
 329             }
 330             break;
 331         case 0x2: // FIFO Control Register (FCR)
 332             break;
 333         case 0x3: // Line Control Register (LCR)
 334             LCR = *(uint8_t*)data;
 335             break;
 336         case 0x4: // Modem Control Register (MCR)
 337             if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
 338                     MCR = 0x9A;
 339             break;
 340         case 0x7: // Scratch Register (SCR)
 341             // We are emulating a 8250 so we don't have a scratch reg
 342             break;
 343         default:
 344             panic("Tried to access a UART port that doesn't exist\n");
 345             break;
 346     }
 347 #endif
 348
 349     return No_Fault;
 350 }
 351
 352 void
 353 Uart::dataAvailable()
 354 {
 355 #ifdef ALPHA_TLASER
 356         platform->postConsoleInt();
 357         status |= RX_INT;
 358 #else
 359
 360     // if the kernel wants an interrupt when we have data
 361     if (IER & UART_IER_RDI)
 362     {
 363         platform->postConsoleInt();
 364         status |= RX_INT;
 365     }
 366
 367 #endif
 368 }
 369
 370 Tick
 371 Uart::cacheAccess(MemReqPtr &req)
 372 {
 373     return curTick + pioLatency;
 374 }
 375
 376 void
 377 Uart::serialize(ostream &os)
 378 {
 379 #ifdef ALPHA_TLASER
 380     SERIALIZE_SCALAR(readAddr);
 381     SERIALIZE_SCALAR(status);
 382 #else
 383     SERIALIZE_SCALAR(status);
 384     SERIALIZE_SCALAR(IER);
 385     SERIALIZE_SCALAR(DLAB);
 386     SERIALIZE_SCALAR(LCR);
 387     SERIALIZE_SCALAR(MCR);
 388     Tick rxintrwhen;
 389     if (rxIntrEvent.scheduled())
 390         rxintrwhen = rxIntrEvent.when();
 391     else
 392         rxintrwhen = 0;
 393     Tick txintrwhen;
 394     if (txIntrEvent.scheduled())
 395         txintrwhen = txIntrEvent.when();
 396     else
 397         txintrwhen = 0;
 398      SERIALIZE_SCALAR(rxintrwhen);
 399      SERIALIZE_SCALAR(txintrwhen);
 400 #endif
 401 }
 402
 403 void
 404 Uart::unserialize(Checkpoint *cp, const std::string &section)
 405 {
 406 #ifdef ALPHA_TLASER
 407     UNSERIALIZE_SCALAR(readAddr);
 408     UNSERIALIZE_SCALAR(status);
 409 #else
 410     UNSERIALIZE_SCALAR(status);
 411     UNSERIALIZE_SCALAR(IER);
 412     UNSERIALIZE_SCALAR(DLAB);
 413     UNSERIALIZE_SCALAR(LCR);
 414     UNSERIALIZE_SCALAR(MCR);
 415     Tick rxintrwhen;
 416     Tick txintrwhen;
 417     UNSERIALIZE_SCALAR(rxintrwhen);
 418     UNSERIALIZE_SCALAR(txintrwhen);
 419     if (rxintrwhen != 0)
 420         rxIntrEvent.schedule(rxintrwhen);
 421     if (txintrwhen != 0)
 422         txIntrEvent.schedule(txintrwhen);
 423 #endif
 424
 425 }
 426
 427 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart)
 428
 429     SimObjectParam<SimConsole *> console;
 430     SimObjectParam<MemoryController *> mmu;
 431     SimObjectParam<Platform *> platform;
 432     Param<Addr> addr;
 433     Param<Addr> size;
 434     SimObjectParam<Bus*> io_bus;
 435     Param<Tick> pio_latency;
 436     SimObjectParam<HierParams *> hier;
 437
 438
 439 END_DECLARE_SIM_OBJECT_PARAMS(Uart)
 440
 441 BEGIN_INIT_SIM_OBJECT_PARAMS(Uart)
 442
 443     INIT_PARAM(console, "The console"),
 444     INIT_PARAM(mmu, "Memory Controller"),
 445     INIT_PARAM(platform, "Pointer to platfrom"),
 446     INIT_PARAM(addr, "Device Address"),
 447     INIT_PARAM_DFLT(size, "Device size", 0x8),
 448     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
 449     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 450     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 451
 452 END_INIT_SIM_OBJECT_PARAMS(Uart)
 453
 454 CREATE_SIM_OBJECT(Uart)
 455 {
 456     return new Uart(getInstanceName(), console, mmu, addr, size, hier, io_bus,
 457                     pio_latency, platform);
 458 }
 459
 460 REGISTER_SIM_OBJECT("Uart", Uart)