Use functions to access XC.
[gem5.git] / dev / uart.hh
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /** @file
30 * Base class for UART
31 */
32
33 #ifndef __UART_HH__
34 #define __UART_HH__
35
36 #include "base/range.hh"
37 #include "dev/io_device.hh"
38
39 class SimConsole;
40 class Platform;
41
42 const int RX_INT = 0x1;
43 const int TX_INT = 0x2;
44
45
46 class Uart : public PioDevice
47 {
48
49 protected:
50 int status;
51 Addr addr;
52 Addr size;
53 SimConsole *cons;
54
55 public:
56 Uart(const std::string &name, SimConsole *c, MemoryController *mmu,
57 Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
58 Platform *p);
59
60 virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
61 virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
62
63
64 /**
65 * Inform the uart that there is data available.
66 */
67 virtual void dataAvailable() = 0;
68
69
70 /**
71 * Return if we have an interrupt pending
72 * @return interrupt status
73 */
74 bool intStatus() { return status ? true : false; }
75
76 /**
77 * Return how long this access will take.
78 * @param req the memory request to calcuate
79 * @return Tick when the request is done
80 */
81 Tick cacheAccess(MemReqPtr &req);
82 };
83
84 #endif // __UART_HH__