dev/uart.hh

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * Defines a 8250 UART
  31  */
  32
  33 #ifndef __TSUNAMI_UART_HH__
  34 #define __TSUNAMI_UART_HH__
  35
  36 #include "dev/tsunamireg.h"
  37 #include "base/range.hh"
  38 #include "dev/io_device.hh"
  39
  40 class SimConsole;
  41 class Platform;
  42
  43 const int RX_INT = 0x1;
  44 const int TX_INT = 0x2;
  45
  46
  47 class Uart : public PioDevice
  48 {
  49
  50   private:
  51     Addr addr;
  52     Addr size;
  53     SimConsole *cons;
  54
  55
  56   protected:
  57     int readAddr; // tlaser only
  58     uint8_t IER, DLAB, LCR, MCR;
  59     int status;
  60
  61     class IntrEvent : public Event
  62     {
  63         protected:
  64             Uart *uart;
  65             int intrBit;
  66         public:
  67             IntrEvent(Uart *u, int bit);
  68             virtual void process();
  69             virtual const char *description();
  70             void scheduleIntr();
  71     };
  72
  73     IntrEvent txIntrEvent;
  74     IntrEvent rxIntrEvent;
  75     Platform *platform;
  76
  77   public:
  78     Uart(const string &name, SimConsole *c, MemoryController *mmu,
  79          Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
  80          Platform *p);
  81
  82     Fault read(MemReqPtr &req, uint8_t *data);
  83     Fault write(MemReqPtr &req, const uint8_t *data);
  84
  85
  86     /**
  87      * Inform the uart that there is data available.
  88      */
  89     void dataAvailable();
  90
  91
  92     /**
  93      * Return if we have an interrupt pending
  94      * @return interrupt status
  95      */
  96     bool intStatus() { return status ? true : false; }
  97
  98     virtual void serialize(std::ostream &os);
  99     virtual void unserialize(Checkpoint *cp, const std::string &section);
 100
 101     /**
 102      * Return how long this access will take.
 103      * @param req the memory request to calcuate
 104      * @return Tick when the request is done
 105      */
 106     Tick cacheAccess(MemReqPtr &req);
 107 };
 108
 109 #endif // __TSUNAMI_UART_HH__