dev/uart8250.cc

   1 /*
   2  * Copyright (c) 2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Implements a 8250 UART
  31  */
  32
  33 #include <string>
  34 #include <vector>
  35
  36 #include "arch/alpha/ev5.hh"
  37 #include "base/inifile.hh"
  38 #include "base/str.hh"        // for to_number
  39 #include "base/trace.hh"
  40 #include "dev/simconsole.hh"
  41 #include "dev/uart8250.hh"
  42 #include "dev/platform.hh"
  43 #include "sim/builder.hh"
  44
  45 using namespace std;
  46 using namespace TheISA;
  47
  48 Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
  49     : Event(&mainEventQueue), uart(u)
  50 {
  51     DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
  52     intrBit = bit;
  53 }
  54
  55 const char *
  56 Uart8250::IntrEvent::description()
  57 {
  58     return "uart interrupt delay event";
  59 }
  60
  61 void
  62 Uart8250::IntrEvent::process()
  63 {
  64     if (intrBit & uart->IER) {
  65        DPRINTF(Uart, "UART InterEvent, interrupting\n");
  66        uart->platform->postConsoleInt();
  67        uart->status |= intrBit;
  68     }
  69     else
  70        DPRINTF(Uart, "UART InterEvent, not interrupting\n");
  71
  72 }
  73
  74 /* The linux serial driver (8250.c about line 1182) loops reading from
  75  * the device until the device reports it has no more data to
  76  * read. After a maximum of 255 iterations the code prints "serial8250
  77  * too much work for irq X," and breaks out of the loop. Since the
  78  * simulated system is so much slower than the actual system, if a
  79  * user is typing on the keyboard it is very easy for them to provide
  80  * input at a fast enough rate to not allow the loop to exit and thus
  81  * the error to be printed. This magic number provides a delay between
  82  * the time the UART receives a character to send to the simulated
  83  * system and the time it actually notifies the system it has a
  84  * character to send to alleviate this problem. --Ali
  85  */
  86 void
  87 Uart8250::IntrEvent::scheduleIntr()
  88 {
  89     static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
  90     DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
  91             curTick + interval);
  92     if (!scheduled())
  93         schedule(curTick + interval);
  94     else
  95         reschedule(curTick + interval);
  96 }
  97
  98
  99 Uart8250::Uart8250(Params *p)
 100     : Uart(p), txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
 101 {
 102     pioSize = 8;
 103
 104     IER = 0;
 105     DLAB = 0;
 106     LCR = 0;
 107     MCR = 0;
 108 }
 109
 110 Tick
 111 Uart8250::read(Packet &pkt)
 112 {
 113     assert(pkt.result == Unknown);
 114     assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
 115     assert(pkt.size == 1);
 116
 117     pkt.time = curTick + pioDelay;
 118     Addr daddr = pkt.addr - pioAddr;
 119     uint8_t *data;
 120
 121     DPRINTF(Uart, " read register %#x\n", daddr);
 122
 123     if (!pkt.data) {
 124         data = new uint8_t;
 125         pkt.data = data;
 126     } else
 127         data = pkt.data;
 128
 129     switch (daddr) {
 130         case 0x0:
 131             if (!(LCR & 0x80)) { // read byte
 132                 if (cons->dataAvailable())
 133                     cons->in(*data);
 134                 else {
 135                     *data = 0;
 136                     // A limited amount of these are ok.
 137                     DPRINTF(Uart, "empty read of RX register\n");
 138                 }
 139                 status &= ~RX_INT;
 140                 platform->clearConsoleInt();
 141
 142                 if (cons->dataAvailable() && (IER & UART_IER_RDI))
 143                     rxIntrEvent.scheduleIntr();
 144             } else { // dll divisor latch
 145                ;
 146             }
 147             break;
 148         case 0x1:
 149             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 150                 *data = IER;
 151             } else { // DLM divisor latch MSB
 152                 ;
 153             }
 154             break;
 155         case 0x2: // Intr Identification Register (IIR)
 156             DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
 157
 158             if (status & RX_INT) /* Rx data interrupt has a higher priority */
 159                 *data = IIR_RXID;
 160             else if (status & TX_INT)
 161                 *data = IIR_TXID;
 162             else
 163                 *data = IIR_NOPEND;
 164
 165             //Tx interrupts are cleared on IIR reads
 166             status &= ~TX_INT;
 167             break;
 168         case 0x3: // Line Control Register (LCR)
 169             *data = LCR;
 170             break;
 171         case 0x4: // Modem Control Register (MCR)
 172             break;
 173         case 0x5: // Line Status Register (LSR)
 174             uint8_t lsr;
 175             lsr = 0;
 176             // check if there are any bytes to be read
 177             if (cons->dataAvailable())
 178                 lsr = UART_LSR_DR;
 179             lsr |= UART_LSR_TEMT | UART_LSR_THRE;
 180             *data = lsr;
 181             break;
 182         case 0x6: // Modem Status Register (MSR)
 183             *data = 0;
 184             break;
 185         case 0x7: // Scratch Register (SCR)
 186             *data = 0; // doesn't exist with at 8250.
 187             break;
 188         default:
 189             panic("Tried to access a UART port that doesn't exist\n");
 190             break;
 191     }
 192 /*    uint32_t d32 = *data;
 193     DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
 194 */
 195     pkt.result = Success;
 196     return pioDelay;
 197 }
 198
 199 Tick
 200 Uart8250::write(Packet &pkt)
 201 {
 202
 203     assert(pkt.result == Unknown);
 204     assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
 205     assert(pkt.size == 1);
 206
 207     pkt.time = curTick + pioDelay;
 208     Addr daddr = pkt.addr - pioAddr;
 209
 210     uint8_t *data = pkt.data;
 211
 212     DPRINTF(Uart, " write register %#x value %#x\n", daddr, *data);
 213
 214     switch (daddr) {
 215         case 0x0:
 216             if (!(LCR & 0x80)) { // write byte
 217                 cons->out(*data);
 218                 platform->clearConsoleInt();
 219                 status &= ~TX_INT;
 220                 if (UART_IER_THRI & IER)
 221                     txIntrEvent.scheduleIntr();
 222             } else { // dll divisor latch
 223                ;
 224             }
 225             break;
 226         case 0x1:
 227             if (!(LCR & 0x80)) { // Intr Enable Register(IER)
 228                 IER = *data;
 229                 if (UART_IER_THRI & IER)
 230                 {
 231                     DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
 232                     txIntrEvent.scheduleIntr();
 233                 }
 234                 else
 235                 {
 236                     DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
 237                     if (txIntrEvent.scheduled())
 238                         txIntrEvent.deschedule();
 239                     if (status & TX_INT)
 240                         platform->clearConsoleInt();
 241                     status &= ~TX_INT;
 242                 }
 243
 244                 if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
 245                     DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
 246                     rxIntrEvent.scheduleIntr();
 247                 } else {
 248                     DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
 249                     if (rxIntrEvent.scheduled())
 250                         rxIntrEvent.deschedule();
 251                     if (status & RX_INT)
 252                         platform->clearConsoleInt();
 253                     status &= ~RX_INT;
 254                 }
 255              } else { // DLM divisor latch MSB
 256                 ;
 257             }
 258             break;
 259         case 0x2: // FIFO Control Register (FCR)
 260             break;
 261         case 0x3: // Line Control Register (LCR)
 262             LCR = *data;
 263             break;
 264         case 0x4: // Modem Control Register (MCR)
 265             if (*data == (UART_MCR_LOOP | 0x0A))
 266                     MCR = 0x9A;
 267             break;
 268         case 0x7: // Scratch Register (SCR)
 269             // We are emulating a 8250 so we don't have a scratch reg
 270             break;
 271         default:
 272             panic("Tried to access a UART port that doesn't exist\n");
 273             break;
 274     }
 275     pkt.result = Success;
 276     return pioDelay;
 277 }
 278
 279 void
 280 Uart8250::dataAvailable()
 281 {
 282     // if the kernel wants an interrupt when we have data
 283     if (IER & UART_IER_RDI)
 284     {
 285         platform->postConsoleInt();
 286         status |= RX_INT;
 287     }
 288
 289 }
 290
 291 void
 292 Uart8250::addressRanges(AddrRangeList &range_list)
 293 {
 294     assert(pioSize != 0);
 295     range_list.clear();
 296     range_list.push_back(RangeSize(pioAddr, pioSize));
 297 }
 298
 299
 300
 301 void
 302 Uart8250::serialize(ostream &os)
 303 {
 304     SERIALIZE_SCALAR(status);
 305     SERIALIZE_SCALAR(IER);
 306     SERIALIZE_SCALAR(DLAB);
 307     SERIALIZE_SCALAR(LCR);
 308     SERIALIZE_SCALAR(MCR);
 309     Tick rxintrwhen;
 310     if (rxIntrEvent.scheduled())
 311         rxintrwhen = rxIntrEvent.when();
 312     else
 313         rxintrwhen = 0;
 314     Tick txintrwhen;
 315     if (txIntrEvent.scheduled())
 316         txintrwhen = txIntrEvent.when();
 317     else
 318         txintrwhen = 0;
 319      SERIALIZE_SCALAR(rxintrwhen);
 320      SERIALIZE_SCALAR(txintrwhen);
 321 }
 322
 323 void
 324 Uart8250::unserialize(Checkpoint *cp, const std::string &section)
 325 {
 326     UNSERIALIZE_SCALAR(status);
 327     UNSERIALIZE_SCALAR(IER);
 328     UNSERIALIZE_SCALAR(DLAB);
 329     UNSERIALIZE_SCALAR(LCR);
 330     UNSERIALIZE_SCALAR(MCR);
 331     Tick rxintrwhen;
 332     Tick txintrwhen;
 333     UNSERIALIZE_SCALAR(rxintrwhen);
 334     UNSERIALIZE_SCALAR(txintrwhen);
 335     if (rxintrwhen != 0)
 336         rxIntrEvent.schedule(rxintrwhen);
 337     if (txintrwhen != 0)
 338         txIntrEvent.schedule(txintrwhen);
 339 }
 340
 341 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 342
 343     Param<Addr> pio_addr;
 344     Param<Tick> pio_latency;
 345     SimObjectParam<Platform *> platform;
 346     SimObjectParam<SimConsole *> sim_console;
 347     SimObjectParam<System *> system;
 348
 349 END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 350
 351 BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
 352
 353     INIT_PARAM(pio_addr, "Device Address"),
 354     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
 355     INIT_PARAM(platform, "platform"),
 356     INIT_PARAM(sim_console, "The Simulator Console"),
 357     INIT_PARAM(system, "system object")
 358
 359 END_INIT_SIM_OBJECT_PARAMS(Uart8250)
 360
 361 CREATE_SIM_OBJECT(Uart8250)
 362 {
 363     Uart8250::Params *p = new Uart8250::Params;
 364     p->name = getInstanceName();
 365     p->pio_addr = pio_addr;
 366     p->pio_delay = pio_latency;
 367     p->platform = platform;
 368     p->cons = sim_console;
 369     p->system = system;
 370     return new Uart8250(p);
 371 }
 372
 373 REGISTER_SIM_OBJECT("Uart8250", Uart8250)
 374