dev/uart8250.hh

   1 /*
   2  * Copyright (c) 2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Defines a 8250 UART
  31  */
  32
  33 #ifndef __TSUNAMI_UART_HH__
  34 #define __TSUNAMI_UART_HH__
  35
  36 #include "dev/tsunamireg.h"
  37 #include "base/range.hh"
  38 #include "dev/io_device.hh"
  39 #include "dev/uart.hh"
  40
  41
  42 /* UART8250 Interrupt ID Register
  43  *  bit 0    Interrupt Pending 0 = true, 1 = false
  44  *  bit 2:1  ID of highest priority interrupt
  45  *  bit 7:3  zeroes
  46  */
  47 #define IIR_NOPEND 0x1
  48
  49 // Interrupt IDs
  50 #define IIR_MODEM 0x00 /* Modem Status (lowest priority) */
  51 #define IIR_TXID  0x02 /* Tx Data */
  52 #define IIR_RXID  0x04 /* Rx Data */
  53 #define IIR_LINE  0x06 /* Rx Line Status (highest priority)*/
  54
  55 class SimConsole;
  56 class Platform;
  57
  58 class Uart8250 : public Uart
  59 {
  60
  61
  62   protected:
  63     uint8_t IER, DLAB, LCR, MCR;
  64
  65     class IntrEvent : public Event
  66     {
  67         protected:
  68             Uart8250 *uart;
  69             int intrBit;
  70         public:
  71             IntrEvent(Uart8250 *u, int bit);
  72             virtual void process();
  73             virtual const char *description();
  74             void scheduleIntr();
  75     };
  76
  77     IntrEvent txIntrEvent;
  78     IntrEvent rxIntrEvent;
  79
  80   public:
  81     Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
  82          Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
  83          Platform *p);
  84
  85     virtual Fault read(MemReqPtr &req, uint8_t *data);
  86     virtual Fault write(MemReqPtr &req, const uint8_t *data);
  87
  88
  89     /**
  90      * Inform the uart that there is data available.
  91      */
  92     virtual void dataAvailable();
  93
  94
  95     /**
  96      * Return if we have an interrupt pending
  97      * @return interrupt status
  98      */
  99     virtual bool intStatus() { return status ? true : false; }
 100
 101     virtual void serialize(std::ostream &os);
 102     virtual void unserialize(Checkpoint *cp, const std::string &section);
 103
 104 };
 105
 106 #endif // __TSUNAMI_UART_HH__