divider.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.decode_types.all;
   8 use work.crhelpers.all;
   9
  10 entity divider is
  11     port (
  12         clk   : in std_logic;
  13         rst   : in std_logic;
  14         d_in  : in Decode2ToDividerType;
  15         d_out : out DividerToWritebackType
  16         );
  17 end entity divider;
  18
  19 architecture behaviour of divider is
  20     signal dend       : std_ulogic_vector(128 downto 0);
  21     signal div        : unsigned(63 downto 0);
  22     signal quot       : std_ulogic_vector(63 downto 0);
  23     signal result     : std_ulogic_vector(63 downto 0);
  24     signal sresult    : std_ulogic_vector(63 downto 0);
  25     signal qbit       : std_ulogic;
  26     signal running    : std_ulogic;
  27     signal signcheck  : std_ulogic;
  28     signal count      : unsigned(6 downto 0);
  29     signal neg_result : std_ulogic;
  30     signal is_modulus : std_ulogic;
  31     signal is_32bit   : std_ulogic;
  32     signal extended   : std_ulogic;
  33     signal is_signed  : std_ulogic;
  34     signal rc         : std_ulogic;
  35     signal write_reg  : std_ulogic_vector(4 downto 0);
  36     signal overflow   : std_ulogic;
  37     signal did_ovf    : std_ulogic;
  38
  39 begin
  40     divider_0: process(clk)
  41     begin
  42         if rising_edge(clk) then
  43             if rst = '1' then
  44                 dend <= (others => '0');
  45                 div <= (others => '0');
  46                 quot <= (others => '0');
  47                 running <= '0';
  48                 count <= "0000000";
  49             elsif d_in.valid = '1' then
  50                 if d_in.is_extended = '1' and not (d_in.is_signed = '1' and d_in.dividend(63) = '1') then
  51                     dend <= '0' & d_in.dividend & x"0000000000000000";
  52                 else
  53                     dend <= '0' & x"0000000000000000" & d_in.dividend;
  54                 end if;
  55                 div <= unsigned(d_in.divisor);
  56                 quot <= (others => '0');
  57                 write_reg <= d_in.write_reg;
  58                 neg_result <= '0';
  59                 is_modulus <= d_in.is_modulus;
  60                 extended <= d_in.is_extended;
  61                 is_32bit <= d_in.is_32bit;
  62                 is_signed <= d_in.is_signed;
  63                 rc <= d_in.rc;
  64                 count <= "1111111";
  65                 running <= '1';
  66                 overflow <= '0';
  67                 signcheck <= d_in.is_signed and (d_in.dividend(63) or d_in.divisor(63));
  68             elsif signcheck = '1' then
  69                 signcheck <= '0';
  70                 neg_result <= dend(63) xor (div(63) and not is_modulus);
  71                 if dend(63) = '1' then
  72                     if extended = '1' then
  73                         dend <= '0' & std_ulogic_vector(- signed(dend(63 downto 0))) & x"0000000000000000";
  74                     else
  75                         dend <= '0' & x"0000000000000000" & std_ulogic_vector(- signed(dend(63 downto 0)));
  76                     end if;
  77                 end if;
  78                 if div(63) = '1' then
  79                     div <= unsigned(- signed(div));
  80                 end if;
  81             elsif running = '1' then
  82                 if count = "0111111" then
  83                     running <= '0';
  84                 end if;
  85                 overflow <= quot(63);
  86                 if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
  87                     dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) &
  88                             dend(63 downto 0) & '0';
  89                     quot <= quot(62 downto 0) & '1';
  90                     count <= count + 1;
  91                 elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
  92                     -- consume 8 bits of zeroes in one cycle
  93                     dend <= dend(120 downto 0) & x"00";
  94                     quot <= quot(55 downto 0) & x"00";
  95                     count <= count + 8;
  96                 else
  97                     dend <= dend(127 downto 0) & '0';
  98                     quot <= quot(62 downto 0) & '0';
  99                     count <= count + 1;
 100                 end if;
 101             else
 102                 count <= "0000000";
 103             end if;
 104         end if;
 105     end process;
 106
 107     divider_1: process(all)
 108     begin
 109         d_out <= DividerToWritebackInit;
 110         d_out.write_reg_nr <= write_reg;
 111
 112         if is_modulus = '1' then
 113             result <= dend(128 downto 65);
 114         else
 115             result <= quot;
 116         end if;
 117         if neg_result = '1' then
 118             sresult <= std_ulogic_vector(- signed(result));
 119         else
 120             sresult <= result;
 121         end if;
 122         did_ovf <= '0';
 123         if is_32bit = '0' then
 124             did_ovf <= overflow or (is_signed and (sresult(63) xor neg_result));
 125         elsif is_signed = '1' then
 126             if overflow = '1' or
 127                 (sresult(63 downto 31) /= x"00000000" & '0' and
 128                  sresult(63 downto 31) /= x"ffffffff" & '1') then
 129                 did_ovf <= '1';
 130             end if;
 131         else
 132             did_ovf <= overflow or (or (sresult(63 downto 32)));
 133         end if;
 134         if did_ovf = '1' then
 135             d_out.write_reg_data <= (others => '0');
 136         elsif (is_32bit = '1') and (is_modulus = '0') then
 137             -- 32-bit divisions set the top 32 bits of the result to 0
 138             d_out.write_reg_data <= x"00000000" & sresult(31 downto 0);
 139         else
 140             d_out.write_reg_data <= sresult;
 141         end if;
 142
 143         if count = "1000000" then
 144             d_out.valid <= '1';
 145             d_out.write_reg_enable <= '1';
 146             if rc = '1' then
 147                 d_out.write_cr_enable <= '1';
 148                 d_out.write_cr_mask <= num_to_fxm(0);
 149                 if (did_ovf = '1') or (or (sresult) = '0') then
 150                     d_out.write_cr_data <= x"20000000";
 151                 elsif (sresult(63) = '1') and not ((is_32bit = '1') and (is_modulus = '0')) then
 152                     d_out.write_cr_data <= x"80000000";
 153                 else
 154                     d_out.write_cr_data <= x"40000000";
 155                 end if;
 156             end if;
 157         end if;
 158     end process;
 159
 160 end architecture behaviour;