2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.decode_types.all;
13 d_in : in Execute1ToDividerType;
14 d_out : out DividerToExecute1Type
18 architecture behaviour of divider is
19 signal dend : std_ulogic_vector(128 downto 0);
20 signal div : unsigned(63 downto 0);
21 signal quot : std_ulogic_vector(63 downto 0);
22 signal result : std_ulogic_vector(63 downto 0);
23 signal sresult : std_ulogic_vector(64 downto 0);
24 signal oresult : std_ulogic_vector(63 downto 0);
25 signal running : std_ulogic;
26 signal count : unsigned(6 downto 0);
27 signal neg_result : std_ulogic;
28 signal is_modulus : std_ulogic;
29 signal is_32bit : std_ulogic;
30 signal extended : std_ulogic;
31 signal is_signed : std_ulogic;
32 signal overflow : std_ulogic;
33 signal ovf32 : std_ulogic;
34 signal did_ovf : std_ulogic;
36 divider_0: process(clk)
38 if rising_edge(clk) then
40 dend <= (others => '0');
41 div <= (others => '0');
42 quot <= (others => '0');
45 elsif d_in.valid = '1' then
46 if d_in.is_extended = '1' then
47 dend <= '0' & d_in.dividend & x"0000000000000000";
49 dend <= '0' & x"0000000000000000" & d_in.dividend;
51 div <= unsigned(d_in.divisor);
52 quot <= (others => '0');
53 neg_result <= d_in.neg_result;
54 is_modulus <= d_in.is_modulus;
55 extended <= d_in.is_extended;
56 is_32bit <= d_in.is_32bit;
57 is_signed <= d_in.is_signed;
62 elsif running = '1' then
63 if count = "0111111" then
67 if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
68 ovf32 <= ovf32 or quot(31);
69 dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) &
70 dend(63 downto 0) & '0';
71 quot <= quot(62 downto 0) & '1';
73 elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
74 -- consume 8 bits of zeroes in one cycle
75 ovf32 <= or (ovf32 & quot(31 downto 24));
76 dend <= dend(120 downto 0) & x"00";
77 quot <= quot(55 downto 0) & x"00";
80 ovf32 <= ovf32 or quot(31);
81 dend <= dend(127 downto 0) & '0';
82 quot <= quot(62 downto 0) & '0';
91 divider_1: process(all)
93 if is_modulus = '1' then
94 result <= dend(128 downto 65);
98 if neg_result = '1' then
99 sresult <= std_ulogic_vector(- signed('0' & result));
101 sresult <= '0' & result;
104 if is_32bit = '0' then
105 did_ovf <= overflow or (is_signed and (sresult(64) xor sresult(63)));
106 elsif is_signed = '1' then
107 if ovf32 = '1' or sresult(32) /= sresult(31) then
113 if did_ovf = '1' then
114 oresult <= (others => '0');
115 elsif (is_32bit = '1') and (is_modulus = '0') then
116 -- 32-bit divisions set the top 32 bits of the result to 0
117 oresult <= x"00000000" & sresult(31 downto 0);
119 oresult <= sresult(63 downto 0);
123 divider_out: process(clk)
125 if rising_edge(clk) then
127 d_out.write_reg_data <= oresult;
128 d_out.overflow <= did_ovf;
129 if count = "1000000" then
135 end architecture behaviour;