2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.decode_types.all;
8 use work.crhelpers.all;
14 d_in : in Decode2ToDividerType;
15 d_out : out DividerToWritebackType
19 architecture behaviour of divider is
20 signal dend : std_ulogic_vector(127 downto 0);
21 signal div : unsigned(63 downto 0);
22 signal quot : std_ulogic_vector(63 downto 0);
23 signal result : std_ulogic_vector(63 downto 0);
24 signal sresult : std_ulogic_vector(63 downto 0);
25 signal qbit : std_ulogic;
26 signal running : std_ulogic;
27 signal count : unsigned(6 downto 0);
28 signal neg_result : std_ulogic;
29 signal is_modulus : std_ulogic;
30 signal is_32bit : std_ulogic;
31 signal rc : std_ulogic;
32 signal write_reg : std_ulogic_vector(4 downto 0);
34 function compare_zero(value : std_ulogic_vector(63 downto 0); is_32 : std_ulogic)
35 return std_ulogic_vector is
38 if value(31) = '1' then
40 elsif unsigned(value(30 downto 0)) > 0 then
46 if value(63) = '1' then
48 elsif unsigned(value(62 downto 0)) > 0 then
54 end function compare_zero;
57 divider_0: process(clk)
59 if rising_edge(clk) then
61 dend <= (others => '0');
62 div <= (others => '0');
63 quot <= (others => '0');
66 elsif d_in.valid = '1' then
67 if d_in.is_extended = '1' then
68 dend <= d_in.dividend & x"0000000000000000";
70 dend <= x"0000000000000000" & d_in.dividend;
72 div <= unsigned(d_in.divisor);
73 quot <= (others => '0');
74 write_reg <= d_in.write_reg;
75 neg_result <= d_in.neg_result;
76 is_modulus <= d_in.is_modulus;
77 is_32bit <= d_in.is_32bit;
81 elsif running = '1' then
82 if count = "0111111" then
85 if dend(127) = '1' or unsigned(dend(126 downto 63)) >= div then
86 dend <= std_ulogic_vector(unsigned(dend(126 downto 63)) - div) &
87 dend(62 downto 0) & '0';
88 quot <= quot(62 downto 0) & '1';
90 elsif dend(127 downto 56) = x"000000000000000000" and count(5 downto 3) /= "111" then
91 -- consume 8 bits of zeroes in one cycle
92 dend <= dend(119 downto 0) & x"00";
93 quot <= quot(55 downto 0) & x"00";
96 dend <= dend(126 downto 0) & '0';
97 quot <= quot(62 downto 0) & '0';
106 divider_1: process(all)
108 d_out <= DividerToWritebackInit;
109 d_out.write_reg_nr <= write_reg;
111 if count(6) = '1' then
113 d_out.write_reg_enable <= '1';
114 if is_modulus = '1' then
115 result <= dend(127 downto 64);
119 if neg_result = '1' then
120 sresult <= std_ulogic_vector(- signed(result));
124 d_out.write_reg_data <= sresult;
126 d_out.write_cr_enable <= '1';
127 d_out.write_cr_mask <= num_to_fxm(0);
128 d_out.write_cr_data <= compare_zero(sresult, is_32bit) & x"0000000";
133 end architecture behaviour;