1 -- Dummy/empty DMI interface to make toplevel happy on unsupported FPGAs
4 use ieee.std_logic_1164.all;
7 use work.wishbone_types.all;
10 generic(ABITS : INTEGER:=8;
13 port(sys_clk : in std_ulogic;
14 sys_reset : in std_ulogic;
15 dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0);
16 dmi_din : in std_ulogic_vector(DBITS - 1 downto 0);
17 dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0);
18 dmi_req : out std_ulogic;
19 dmi_wr : out std_ulogic;
20 dmi_ack : in std_ulogic
24 architecture behaviour of dmi_dtm is
26 dmi_addr <= (others => '0');
27 dmi_dout <= (others => '0');
30 end architecture behaviour;