dmi_dtm_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 library unisim;
  10 use unisim.vcomponents.all;
  11
  12 entity dmi_dtm_tb is
  13 end dmi_dtm_tb;
  14
  15 architecture behave of dmi_dtm_tb is
  16     signal clk           : std_ulogic;
  17     signal rst           : std_ulogic;
  18     constant clk_period  : time := 10 ns;
  19     constant jclk_period : time := 30 ns;
  20
  21     -- DMI debug bus signals
  22     signal dmi_addr     : std_ulogic_vector(7 downto 0);
  23     signal dmi_din      : std_ulogic_vector(63 downto 0);
  24     signal dmi_dout     : std_ulogic_vector(63 downto 0);
  25     signal dmi_req      : std_ulogic;
  26     signal dmi_wr       : std_ulogic;
  27     signal dmi_ack      : std_ulogic;
  28
  29     -- Global JTAG signals (used by BSCANE2 inside dmi_dtm
  30     alias j : glob_jtag_t is glob_jtag;
  31
  32     -- Wishbone interfaces
  33     signal wishbone_ram_in : wishbone_slave_out;
  34     signal wishbone_ram_out : wishbone_master_out;
  35
  36 begin
  37     dtm: entity work.dmi_dtm
  38         generic map(
  39             ABITS => 8,
  40             DBITS => 64
  41             )
  42         port map(
  43             sys_clk     => clk,
  44             sys_reset   => rst,
  45             dmi_addr    => dmi_addr,
  46             dmi_din     => dmi_din,
  47             dmi_dout    => dmi_dout,
  48             dmi_req     => dmi_req,
  49             dmi_wr      => dmi_wr,
  50             dmi_ack     => dmi_ack
  51             );
  52
  53     simple_ram_0: entity work.wishbone_bram_wrapper
  54         generic map(RAM_INIT_FILE => "main_ram.bin",
  55                     MEMORY_SIZE => 524288)
  56         port map(clk => clk, rst => rst,
  57                  wishbone_in => wishbone_ram_out,
  58                  wishbone_out => wishbone_ram_in);
  59
  60     wishbone_debug_0: entity work.wishbone_debug_master
  61         port map(clk => clk, rst => rst,
  62                  dmi_addr => dmi_addr(1 downto 0),
  63                  dmi_dout => dmi_din,
  64                  dmi_din => dmi_dout,
  65                  dmi_wr => dmi_wr,
  66                  dmi_ack => dmi_ack,
  67                  dmi_req => dmi_req,
  68                  wb_in => wishbone_ram_in,
  69                  wb_out => wishbone_ram_out);
  70
  71     -- system clock
  72     sys_clk: process
  73     begin
  74         clk <= '1';
  75         wait for clk_period / 2;
  76         clk <= '0';
  77         wait for clk_period / 2;
  78     end process sys_clk;
  79
  80     -- system sim: just reset and wait
  81     sys_sim: process
  82     begin
  83         rst <= '1';
  84         wait for clk_period;
  85         rst <= '0';
  86         wait;
  87     end process;
  88
  89     -- jtag sim process
  90     sim_jtag: process
  91         procedure clock(count: in INTEGER) is
  92         begin
  93             for i in 1 to count loop
  94                 j.tck <= '0';
  95                 wait for jclk_period/2;
  96                 j.tck <= '1';
  97                 wait for jclk_period/2;
  98             end loop;
  99         end procedure clock;
 100
 101         procedure shift_out(val: in std_ulogic_vector) is
 102         begin
 103             for i in 0 to val'length-1 loop
 104                 j.tdi <= val(i);
 105                 clock(1);
 106             end loop;
 107         end procedure shift_out;
 108
 109         procedure shift_in(val: out std_ulogic_vector) is
 110         begin
 111             for i in val'length-1 downto 0 loop
 112                 val := j.tdo & val(val'length-1 downto 1);
 113                 clock(1);
 114             end loop;
 115         end procedure shift_in;
 116
 117         procedure send_command(
 118             addr : in std_ulogic_vector(7 downto 0);
 119             data : in std_ulogic_vector(63 downto 0);
 120             op   : in std_ulogic_vector(1 downto 0)) is
 121         begin
 122             j.capture <= '1';
 123             clock(1);
 124             j.capture <= '0';
 125             clock(1);
 126             j.shift <= '1';
 127             shift_out(op);
 128             shift_out(data);
 129             shift_out(addr);
 130             j.shift <= '0';
 131             j.update <= '1';
 132             clock(1);
 133             j.update <= '0';
 134             clock(1);
 135         end procedure send_command;
 136
 137         procedure read_resp(
 138             op   : out std_ulogic_vector(1 downto 0);
 139             data : out std_ulogic_vector(63 downto 0)) is
 140
 141             variable addr : std_ulogic_vector(7 downto 0);
 142         begin
 143             j.capture <= '1';
 144             clock(1);
 145             j.capture <= '0';
 146             clock(1);
 147             j.shift <= '1';
 148             shift_in(op);
 149             shift_in(data);
 150             shift_in(addr);
 151             j.shift <= '0';
 152             j.update <= '1';
 153             clock(1);
 154             j.update <= '0';
 155             clock(1);
 156         end procedure read_resp;
 157
 158         procedure dmi_write(addr : in std_ulogic_vector(7 downto 0);
 159                             data : in std_ulogic_vector(63 downto 0)) is
 160             variable resp_op   : std_ulogic_vector(1 downto 0);
 161             variable resp_data : std_ulogic_vector(63 downto 0);
 162             variable timeout   : integer;
 163         begin
 164             send_command(addr, data, "10");
 165             loop
 166                 read_resp(resp_op, resp_data);
 167                 case resp_op is
 168                 when "00" =>
 169                     return;
 170                 when "11" =>
 171                     timeout := timeout + 1;
 172                     assert timeout < 0
 173                         report "dmi_write timed out !" severity error;
 174                 when others =>
 175                     assert 0 > 1 report "dmi_write got odd status: " &
 176                         to_hstring(resp_op) severity error;
 177                 end case;
 178             end loop;
 179         end procedure dmi_write;
 180
 181
 182         procedure dmi_read(addr : in std_ulogic_vector(7 downto 0);
 183                            data : out std_ulogic_vector(63 downto 0)) is
 184             variable resp_op   : std_ulogic_vector(1 downto 0);
 185             variable timeout   : integer;
 186         begin
 187             send_command(addr, (others => '0'), "01");
 188             loop
 189                 read_resp(resp_op, data);
 190                 case resp_op is
 191                 when "00" =>
 192                     return;
 193                 when "11" =>
 194                     timeout := timeout + 1;
 195                     assert timeout < 0
 196                         report "dmi_read timed out !" severity error;
 197                 when others =>
 198                     assert 0 > 1 report "dmi_read got odd status: " &
 199                         to_hstring(resp_op) severity error;
 200                 end case;
 201             end loop;
 202         end procedure dmi_read;
 203
 204         variable data : std_ulogic_vector(63 downto 0);
 205     begin
 206         -- init & reset
 207         j.reset <= '1';
 208         j.sel <= "0000";
 209         j.capture <= '0';
 210         j.update <= '0';
 211         j.shift <= '0';
 212         j.tdi <= '0';
 213         j.tms <= '0';
 214         j.runtest <= '0';
 215         clock(5);
 216         j.reset <= '0';
 217         clock(5);
 218
 219         -- select chain 2
 220         j.sel <= "0010";
 221         clock(1);
 222
 223         -- send command
 224         dmi_read(x"00", data);
 225         report "Read addr reg:" & to_hstring(data);
 226         report "Writing addr reg to all 1's";
 227         dmi_write(x"00", (others => '1'));
 228         dmi_read(x"00", data);
 229         report "Read addr reg:" & to_hstring(data);
 230
 231         report "Writing ctrl reg to all 1's";
 232         dmi_write(x"02", (others => '1'));
 233         dmi_read(x"02", data);
 234         report "Read ctrl reg:" & to_hstring(data);
 235
 236         report "Read memory at 0...\n";
 237         dmi_write(x"00", x"0000000000000000");
 238         dmi_write(x"02", x"00000000000007ff");
 239         dmi_read(x"01", data);
 240         report "00:" & to_hstring(data);
 241         dmi_read(x"01", data);
 242         report "08:" & to_hstring(data);
 243         dmi_read(x"01", data);
 244         report "10:" & to_hstring(data);
 245         dmi_read(x"01", data);
 246         report "18:" & to_hstring(data);
 247         clock(10);
 248         std.env.finish;
 249     end process;
 250 end behave;