1 -- Xilinx internal JTAG to DMI interface
5 -- req : ____/------------\_____
9 -- din : xxxxxxxxxxxx< >xxx
10 -- ack : ____________/------\___
12 -- * addr/dout set along with req, can be latched on same cycle by slave
13 -- * ack & din remain up until req is dropped by master, the slave must
14 -- provide a stable output on din on reads during that time.
15 -- * req remains low at until at least one sysclk after ack seen down.
17 -- JTAG (tck) DMI (sys_clk)
21 -- (jtag_req_1) -> * dmi_req = 1 >
26 -- * jtag_req = 0 (and latch dmi_din)
28 -- (jtag_req_1) -> * dmi_req = 0 >
33 -- jtag_req can go back to 1 when jtag_rsp_1 is 0
36 -- - I use 2 flip fops for sync, is that enough ?
37 -- - I treat the jtag_reset as an async reset, is that necessary ?
38 -- - Dbl check reset situation since we have two different resets
39 -- each only resetting part of the logic...
40 -- - Look at optionally removing the synchronizer on the ack path,
41 -- assuming JTAG is always slow enough that ack will have been
42 -- stable long enough by the time CAPTURE comes in.
43 -- - We could avoid the latched request by not shifting while a
44 -- request is in progress (and force TDO to 1 to return a busy
47 -- WARNING: This isn't the real DMI JTAG protocol (at least not yet).
48 -- a command while busy will be ignored. A response of "11"
49 -- means the previous command is still going, try again.
50 -- As such We don't implement the DMI "error" status, and
51 -- we don't implement DTMCS yet... This may still all change
52 -- but for now it's easier that way as the real DMI protocol
53 -- requires for a command to work properly that enough TCK
54 -- are sent while IDLE and I'm having trouble getting that
55 -- working with UrJtag and the Xilinx BSCAN2 for now.
58 use ieee.std_logic_1164.all;
59 use ieee.math_real.all;
62 use work.wishbone_types.all;
65 use unisim.vcomponents.all;
68 generic(ABITS : INTEGER:=8;
71 port(sys_clk : in std_ulogic;
72 sys_reset : in std_ulogic;
73 dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0);
74 dmi_din : in std_ulogic_vector(DBITS - 1 downto 0);
75 dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0);
76 dmi_req : out std_ulogic;
77 dmi_wr : out std_ulogic;
78 dmi_ack : in std_ulogic
79 -- dmi_err : in std_ulogic TODO: Add error response
83 architecture behaviour of dmi_dtm is
85 -- Signals coming out of the BSCANE2 block
86 signal jtag_reset : std_ulogic;
87 signal capture : std_ulogic;
88 signal update : std_ulogic;
89 signal drck : std_ulogic;
90 signal jtag_clk : std_ulogic;
91 signal sel : std_ulogic;
92 signal shift : std_ulogic;
93 signal tdi : std_ulogic;
94 signal tdo : std_ulogic;
95 signal tck : std_ulogic;
97 -- ** JTAG clock domain **
100 signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
103 signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
105 -- A request is present
106 signal jtag_req : std_ulogic;
108 -- Synchronizer for jtag_rsp (sys clk -> jtag_clk)
109 signal dmi_ack_0 : std_ulogic;
110 signal dmi_ack_1 : std_ulogic;
112 -- ** sys clock domain **
114 -- Synchronizer for jtag_req (jtag clk -> sys clk)
115 signal jtag_req_0 : std_ulogic;
116 signal jtag_req_1 : std_ulogic;
118 -- ** combination signals
119 signal jtag_bsy : std_ulogic;
120 signal op_valid : std_ulogic;
121 signal rsp_op : std_ulogic_vector(1 downto 0);
124 constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00";
125 constant DMI_REQ_RD : std_ulogic_vector(1 downto 0) := "01";
126 constant DMI_REQ_WR : std_ulogic_vector(1 downto 0) := "10";
127 constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00";
128 constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
132 -- Implement the Xilinx bscan2 for series 7 devices (TODO: use PoC to
133 -- wrap this if compatibility is required with older devices).
152 -- Some examples out there suggest buffering the clock so it's
153 -- treated as a proper clock net. This is probably needed when using
154 -- drck (the gated clock) but I'm using the real tck here to avoid
155 -- missing the update phase so maybe not...
165 -- dmi_req synchronization
166 dmi_req_sync : process(sys_clk)
168 -- sys_reset is synchronous
169 if rising_edge(sys_clk) then
170 if (sys_reset = '1') then
174 jtag_req_0 <= jtag_req;
175 jtag_req_1 <= jtag_req_0;
179 dmi_req <= jtag_req_1;
181 -- dmi_ack synchronization
182 dmi_ack_sync: process(jtag_clk, jtag_reset)
184 -- jtag_reset is async (see comments)
185 if jtag_reset = '1' then
188 elsif rising_edge(jtag_clk) then
189 dmi_ack_0 <= dmi_ack;
190 dmi_ack_1 <= dmi_ack_0;
194 -- jtag_bsy indicates whether we can start a new request, we can when
195 -- we aren't already processing one (jtag_req) and the synchronized ack
196 -- of the previous one is 0.
198 jtag_bsy <= jtag_req or dmi_ack_1;
200 -- decode request type in shift register
201 with shiftr(1 downto 0) select op_valid <=
206 -- encode response op
207 rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK;
209 -- Some DMI out signals are directly driven from the request register
210 dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2);
211 dmi_dout <= request(DBITS + 1 downto 2);
212 dmi_wr <= '1' when request(1 downto 0) = DMI_REQ_WR else '0';
214 -- TDO is wired to shift register bit 0
217 -- Main state machine. Handles shift registers, request latch and
218 -- jtag_req latch. Could be split into 3 processes but it's probably
221 shifter: process(jtag_clk, jtag_reset)
223 if jtag_reset = '1' then
224 shiftr <= (others => '0');
225 request <= (others => '0');
227 elsif rising_edge(jtag_clk) then
229 -- Handle jtag "commands" when sel is 1
231 -- Shift state, rotate the register
233 shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1);
236 -- Update state (trigger)
238 -- Latch the request if we aren't already processing one and
239 -- it has a valid command opcode.
241 if update = '1' and op_valid = '1' then
242 if jtag_bsy = '0' then
246 -- Set the shift register "op" to "busy". This will prevent
247 -- us from re-starting the command on the next update if
248 -- the command completes before that.
249 shiftr(1 downto 0) <= DMI_RSP_BSY;
252 -- Request completion.
254 -- Capture the response data for reads and clear request flag.
256 -- Note: We clear req (and thus dmi_req) here which relies on tck
257 -- ticking and sel set. This means we are stuck with dmi_req up if
258 -- the jtag interface stops. Slaves must be resilient to this.
260 if jtag_req = '1' and dmi_ack_1 = '1' then
262 if request(1 downto 0) = DMI_REQ_RD then
263 request(DBITS + 1 downto 2) <= dmi_din;
267 -- Capture state, grab latch content with updated status
268 if capture = '1' then
269 shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op;
275 end architecture behaviour;