docs/pinmux.mdwn

   1 # Pinmux, IO Pads, and JTAG Boundary scan
   2
   3 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
   4 An FPGA has built-in IO Pads, the wires terminate inside an
   5 existing silicon block which has been tested for you.
   6
   7 Designing an ASIC, there is no guarantee that the IO pad is
   8 working when manufactured. Worse, the peripheral could be
   9 faulty.  How can you tell what the cause is? There are two
  10 possible faults, but only one symptom ("it dunt wurk").
  11 This problem is what JTAG Boundary Scan is designed to solve.
  12 JTAG can be operated
  13 at very low clock frequencies (5 khz is perfectly acceptable)
  14 so there is very little risk of clock skew during that testing.
  15
  16
  17 <img src="https://libre-soc.org/shakti/m_class/JTAG/jtag-block.jpg"
  18   width=600 />
  19