docs/pinmux.mdwn

   1 # Pinmux, IO Pads, and JTAG Boundary scan
   2
   3 Links:
   4
   5 * <http://www2.eng.cam.ac.uk/~dmh/4b7/resource/section14.htm>
   6 * <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=50>
   8 * <https://git.libre-soc.org/?p=c4m-jtag.git;a=tree;hb=HEAD>
   9
  10 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
  11 An FPGA has built-in IO Pads, the wires terminate inside an
  12 existing silicon block which has been tested for you.
  13 In an ASIC, you are going to have to do everything yourself.
  14 In an ASIC, a bi-directional IO Pad requires three wires (in, out,
  15 out-enable) to be routed right the way from the ASIC, all
  16 the way to the IO PAD, where only then does a wire bond connect
  17 it to a single pin.
  18
  19 [[!img CH02-44.gif]]
  20
  21 Designing an ASIC, there is no guarantee that the IO pad is
  22 working when manufactured. Worse, the peripheral could be
  23 faulty.  How can you tell what the cause is? There are two
  24 possible faults, but only one symptom ("it dunt wurk").
  25 This problem is what JTAG Boundary Scan is designed to solve.
  26 JTAG can be operated from an external digital clock,
  27 at very low frequencies (5 khz is perfectly acceptable)
  28 so there is very little risk of clock skew during that testing.
  29
  30 Additionally, an SoC is designed to be low cost, to use low cost
  31 packaging. ASICs are typically 32 to 128 pins QFP
  32 only in the Embedded
  33 Controller range, and between 300 to 650 FBGA in the Tablet /
  34 Smartphone range, absolute maximum of 19 mm on a side.
  35 1,000 pin packages common to Intel desktop processors are
  36 absolutely out of the question.
  37
  38 (*With each pin wire bond smashing
  39 into the ASIC using purely heat of impact to melt the wire,
  40 cracks in the die can occur. The more times
  41 the bonding equipment smashes into the die, the higher the
  42 chances of irreversible damage, hence why larger pin packaged
  43 ASICs are much more expensive: not because of their manufacturing
  44 cost but because far more of them fail due to having been
  45 literally hit with a hammer many more times*)
  46
  47 Yet, the expectation from the market is to be able to fit 1,000++
  48 pins worth of peripherals into only 200 to 400 worth of actual
  49 IO Pads. The solution here: a GPIO Pinmux, described in some
  50 detail here <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
  51
  52 This page goes over the details and issues involved in creating
  53 an ASIC that combines **both** JTAG Boundary Scan **and** GPIO
  54 Muxing, down to layout considerations using coriolis2.
  55
  56 # JTAG Boundary Scan
  57
  58 JTAG Scanning is a (paywalled) IEEE Standard: 1149.1 which with
  59 a little searching can be found online.  Its purpose is to allow
  60 a well-defined method of testing ASIC IO pads that a Foundry or
  61 ASIC test house may apply easily with off-the-shelf equipment.
  62 Scan chaining can also connect multiple ASICs together so that
  63 the same test can be run on a large batch of ASICs at the same
  64 time.
  65
  66 IO Pads come in four primary different types:
  67
  68 * Input
  69 * Output
  70 * Output with Tristate (enable)
  71 * Bi-directional Input/Output with direction enable
  72
  73 Interestingly these can all be synthesised from one
  74 Bi-directional IO Pad.  Other features such as Differential
  75 Pairs may also be constructed from an inverter and a pair
  76 of IO Pads.  Other more advanced features include pull-up
  77 and pull-down resistors, Schmidt triggering for interrupts,
  78 different drive strengths, and so on, but the basics are
  79 that the Pad is either an input, or an output, or both.
  80
  81 The JTAG Boundary Scan therefore needs to know what type
  82 each pad is (In/Out/Bi) and has to "insert" itself in between
  83 the wires, which may be just an input, or just an output,
  84 and, if bi-directional, an "output enable" line.
  85
  86 The "insertion" (or, "Tap") into those wires requires a
  87 pair of Muxes for each wire.  Under normal operation
  88 the Muxes bypass JTAG entirely: the IO Pad is connected
  89 directly to the Core (a hardware term for a "peripheral",
  90 in Software terminology).
  91
  92 When JTAG Scan is enabled, then for every pin that is
  93 "tapped into", the Muxes flip such that:
  94
  95 * The IO Pad is connected directly to latches controlled
  96   by the JTAG Shift Register
  97 * The Core (peripheral) likewise but to *different bits*
  98   from those that the Pad is connected to
  99
 100 In this way, not only can JTAG control or read the IO Pad,
 101 but it can also read or control the Core (peripheral).
 102 This is its entire purpose: to allow for the detection
 103 and triaging of faults.
 104
 105 * Software may be uploaded and run which sets a bit on
 106   one of the peripheral outputs (UART Tx for example).
 107   If the UART TX IO Pad was faulty, no possibility existd
 108   without Boundary Scan to determine if the peripheral
 109   was at fault.  With the UART TX pin function being
 110   redirected to a JTAG Shift Register, the results of the
 111   software setting UART Tx may be detected by checking
 112   the appropriate Shift Register bit.
 113 * Likewise, a voltage may be applied to the UART RX Pad,
 114   and the corresponding SR bit checked to see if the
 115   pad is working.  If the UART Rx peripheral was faulty
 116   this would not be possible.
 117
 118 <img src="https://libre-soc.org/shakti/m_class/JTAG/jtag-block.jpg"
 119   width=500 />
 120
 121 [[!img gpio_block.png]]