docs/pinmux.mdwn

   1 # Pinmux, IO Pads, and JTAG Boundary scan
   2
   3 Links:
   4
   5 * <http://www2.eng.cam.ac.uk/~dmh/4b7/resource/section14.htm>
   6 * <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=50>
   8
   9 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
  10 An FPGA has built-in IO Pads, the wires terminate inside an
  11 existing silicon block which has been tested for you.  In an
  12 ASIC, a bi-directional IO Pad requires three wires (in, out,
  13 out-enable) to be routed right the way from the ASIC, all
  14 the way to the IO PAD, where only then does a wire bond connect
  15 it to a single pin.
  16
  17 [[!img CH02-44.gif]]
  18
  19 Designing an ASIC, there is no guarantee that the IO pad is
  20 working when manufactured. Worse, the peripheral could be
  21 faulty.  How can you tell what the cause is? There are two
  22 possible faults, but only one symptom ("it dunt wurk").
  23 This problem is what JTAG Boundary Scan is designed to solve.
  24 JTAG can be operated from an external digital clock,
  25 at very low frequencies (5 khz is perfectly acceptable)
  26 so there is very little risk of clock skew during that testing.
  27
  28 Additionally, an SoC is designed to be low cost, to use low cost
  29 packaging. ASICs are typically 32 to 128 pins QFP
  30 only in the Embedded
  31 Controller range, and between 300 to 650 FBGA in the Tablet /
  32 Smartphone range, absolute maximum of 19 mm on a side.
  33 1,000 pin packages common to Intel desktop processors are
  34 absolutely out of the question.
  35
  36 (*With each pin wire bond smashing
  37 into the ASIC using purely heat of impact to melt the wire,
  38 cracks in the die can occur. The more times
  39 the bonding equipment smashes into the die, the higher the
  40 chances of irreversible damage, hence why larger pin packaged
  41 ASICs are much more expensive: not because of their manufacturing
  42 cost but because far more of them fail due to having been
  43 literally hit with a hammer many more times*)
  44
  45 Yet, the expectation from the market is to be able to fit 1,000++
  46 pins worth of peripherals into only 200 to 400 worth of actual
  47 IO Pads. The solution here: a GPIO Pinmux, described in some
  48 detail here <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
  49
  50 This page goes over the details and issues involved in creating
  51 an ASIC that combines **both** JTAG Boundary Scan **and** GPIO
  52 Muxing, down to layout considerations using coriolis2.
  53
  54 <img src="https://libre-soc.org/shakti/m_class/JTAG/jtag-block.jpg"
  55   width=500 />
  56
  57 [[!img gpio_block.png]]