docs/relnotes/11.0.8.rst

   1 Mesa 11.0.8 Release Notes / December 9, 2015
   2 ============================================
   3
   4 Mesa 11.0.8 is a bug fix release which fixes bugs found since the 11.0.7
   5 release.
   6
   7 Mesa 11.0.8 implements the OpenGL 4.1 API, but the version reported by
   8 glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
   9 glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being
  10 used. Some drivers don't support all the features required in OpenGL
  11 4.1. OpenGL 4.1 is **only** available if requested at context creation
  12 because compatibility contexts are not supported.
  13
  14 SHA256 checksums
  15 ----------------
  16
  17 ::
  18
  19    ab9db87b54d7525e4b611b82577ea9a9eae55927558df57b190059d5ecd9406f  mesa-11.0.8.tar.gz
  20    5696e4730518b6805d2ed5def393c4293f425a2c2c01bd5ed4bdd7ad62f7ad75  mesa-11.0.8.tar.xz
  21
  22 New features
  23 ------------
  24
  25 None
  26
  27 Bug fixes
  28 ---------
  29
  30 This list is likely incomplete.
  31
  32 -  `Bug 91806 <https://bugs.freedesktop.org/show_bug.cgi?id=91806>`__ -
  33    configure does not test whether assembler supports sse4.1
  34 -  `Bug 92849 <https://bugs.freedesktop.org/show_bug.cgi?id=92849>`__ -
  35    [IVB HSW BDW] piglit image load/store
  36    load-from-cleared-image.shader_test fails
  37 -  `Bug 92909 <https://bugs.freedesktop.org/show_bug.cgi?id=92909>`__ -
  38    Offset/alignment issue with layout std140 and vec3
  39 -  `Bug 93004 <https://bugs.freedesktop.org/show_bug.cgi?id=93004>`__ -
  40    Guild Wars 2 crash on nouveau DX11 cards
  41 -  `Bug 93215 <https://bugs.freedesktop.org/show_bug.cgi?id=93215>`__ -
  42    [Regression bisected] Ogles1conform Automatic mipmap generation test
  43    is fail
  44 -  `Bug 93266 <https://bugs.freedesktop.org/show_bug.cgi?id=93266>`__ -
  45    gl_arb_shading_language_420pack does not allow binding of image
  46    variables
  47
  48 Changes
  49 -------
  50
  51 Boyuan Zhang (1):
  52
  53 -  radeon/uvd: uv pitch separation for stoney
  54
  55 Dave Airlie (9):
  56
  57 -  r600: do SQ flush ES ring rolling workaround
  58 -  r600: SMX returns CONTEXT_DONE early workaround
  59 -  r600/shader: split address get out to a function.
  60 -  r600/shader: add utility functions to do single slot arithmatic
  61 -  r600g: fix geom shader input indirect indexing.
  62 -  r600: handle geometry dynamic input array index
  63 -  radeonsi: handle doubles in lds load path.
  64 -  mesa/varray: set double arrays to non-normalised.
  65 -  mesa/shader: return correct attribute location for double matrix
  66    arrays
  67
  68 Emil Velikov (8):
  69
  70 -  docs: add sha256 checksums for 11.0.7
  71 -  cherry-ignore: don't pick a specific i965 formats patch
  72 -  Revert "i965/nir: Remove unused indirect handling"
  73 -  Revert "i965/state: Get rid of dword_pitch arguments to buffer
  74    functions"
  75 -  Revert "i965/vec4: Use a stride of 1 and byte offsets for UBOs"
  76 -  Revert "i965/fs: Use a stride of 1 and byte offsets for UBOs"
  77 -  Revert "i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge"
  78 -  Update version to 11.0.8
  79
  80 Francisco Jerez (1):
  81
  82 -  i965: Resolve color and flush for all active shader images in
  83    intel_update_state().
  84
  85 Ian Romanick (1):
  86
  87 -  meta/generate_mipmap: Work-around GLES 1.x problem with
  88    GL_DRAW_FRAMEBUFFER
  89
  90 Ilia Mirkin (17):
  91
  92 -  freedreno/a4xx: support lod_bias
  93 -  freedreno/a4xx: fix 5_5_5_1 texture sampler format
  94 -  freedreno/a4xx: point regid to "red" even for alpha-only rb formats
  95 -  nvc0/ir: fold postfactor into immediate
  96 -  nv50/ir: deal with loops with no breaks
  97 -  nv50/ir: the mad source might not have a defining instruction
  98 -  nv50/ir: fix instruction permutation logic
  99 -  nv50/ir: don't forget to mark flagsDef on cvt in txb lowering
 100 -  nv50/ir: fix DCE to not generate 96-bit loads
 101 -  nv50/ir: avoid looking at uninitialized srcMods entries
 102 -  gk110/ir: fix imul hi emission with limm arg
 103 -  gk104/ir: sampler doesn't matter for txf
 104 -  gk110/ir: fix imad sat/hi flag emission for immediate args
 105 -  nv50/ir: fix cutoff for using r63 vs r127 when replacing zero
 106 -  nv50/ir: can't have predication and immediates
 107 -  glsl: assign varying locations to tess shaders when doing SSO
 108 -  ttn: add TEX2 support
 109
 110 Jason Ekstrand (5):
 111
 112 -  i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge
 113 -  i965/fs: Use a stride of 1 and byte offsets for UBOs
 114 -  i965/vec4: Use a stride of 1 and byte offsets for UBOs
 115 -  i965/state: Get rid of dword_pitch arguments to buffer functions
 116 -  i965/nir: Remove unused indirect handling
 117
 118 Jonathan Gray (2):
 119
 120 -  configure.ac: use pkg-config for libelf
 121 -  configure: check for python2.7 for PYTHON2
 122
 123 Kenneth Graunke (2):
 124
 125 -  i965: Fix fragment shader struct inputs.
 126 -  i965: Fix scalar vertex shader struct outputs.
 127
 128 Marek Olšák (8):
 129
 130 -  radeonsi: fix occlusion queries on Fiji
 131 -  radeonsi: fix a hang due to uninitialized border color registers
 132 -  radeonsi: fix Fiji for LLVM <= 3.7
 133 -  radeonsi: don't call of u_prims_for_vertices for patches and
 134    rectangles
 135 -  radeonsi: apply the streamout workaround to Fiji as well
 136 -  gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1
 137    correctly
 138 -  tgsi/scan: add flag colors_written
 139 -  r600g: write all MRTs only if there is exactly one output (fixes a
 140    hang)
 141
 142 Matt Turner (1):
 143
 144 -  glsl: Allow binding of image variables with 420pack.
 145
 146 Neil Roberts (2):
 147
 148 -  i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format
 149 -  i965: Add B8G8R8X8_SRGB to the alpha format override
 150
 151 Oded Gabbay (1):
 152
 153 -  configura.ac: fix test for SSE4.1 assembler support
 154
 155 Patrick Rudolph (2):
 156
 157 -  nv50,nvc0: fix use-after-free when vertex buffers are unbound
 158 -  gallium/util: return correct number of bound vertex buffers
 159
 160 Samuel Pitoiset (1):
 161
 162 -  nvc0: free memory allocated by the prog which reads MP perf counters
 163
 164 Tapani Pälli (1):
 165
 166 -  i965: use \_Shader to get fragment program when updating surface
 167    state
 168
 169 Tom Stellard (2):
 170
 171 -  radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}
 172 -  radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC\* register
 173    values